THS8083APZP datasheet(33/63 Pages) TI

33 / 63 page

3−20

3.11.38 Register Name: CH3_CLP

Subaddress: 2B (R/W)

CH3_CLP7

MSB

LSB

CH3_CLP6

CH3_CLP5

CH3_CLP4

CH3_CLP3

CH3_CLP2

CH3_CLP1

CH3_CLP0

CH3_CLP[7..0]

Programmable clamp value for channel 3

Default: 0x80 = 128 (mid-range)

3.11.39 Register Name: CH3_COARSE

Subaddress: 2C (R/W)

MSB

LSB

CH3_COARSE5 CH3_COARSE4 CH3_COARSE3 CH3_COARSE2 CH3_COARSE1 CH3_COARSE0

CH3_COARSE[5..0]

Coarse PGA value for channel 3

Default: 0x20 = 32 (mid-range)

3.11.40 Register Name: CH3_FINE

Subaddress: 2D (R/W)

MSB

LSB

CH3_FINE4

CH3_FINE3

CH3_FINE2

CH3_FINE1

CH3_FINE0

CH3_FINE[4..0]

Fine PGA value for channel 3

Default: 0x10 = 16 (mid-range)

3.11.41 Register Name: PIX_TRAP_0

Subaddress: 2E (R/W)

PIX_TRAP7

MSB

LSB

PIX_TRAP6

PIX_TRAP5

PIX_TRAP4

PIX_TRAP3

PIX_TRAP2

PIX_TRAP1

PIX_TRAP0

PIX_TRAP[7..0]

PIX_TRAP[10..0] sets the pixel count value in a line to be sampled. Each <PIX_TRAP>th value on each line

is stored in the CH<n>_RDBK registers

Default: 0x04

3.11.42 Register Name: PIX_TRAP_1

Subaddress: 2F (R/W)

MSB

LSB

PIX_TRAP10

PIX_TRAP9

PIX_TRAP8

PIX_TRAP11

PIX_TRAP[11..8]:

See register PIX_TRAP_0

Default: 0x00

3.11.43 Register Name: PWDN_CTRL

Subaddress: 30 (R/W)

MSB

LSB

PWDN_ALL

PWDN_REF

PWDN_BGAP

DTO_DIS

PWDN_ALL

Powers down complete chip excluding I2C, clamping, and composite sync slicer. Enables green mode for

monitor standby.

0 = active (default)

1 = powered down

THS8083APZP датащи(PDF) 33 Page - Texas Instruments

THS8083APZP датащи(HTML) 33 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

датащи скачать

ссылки URL