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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AMD-K6 датащи(PDF) 43 Page - Advanced Micro Devices |
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AMD-K6 датащи(HTML) 43 Page - Advanced Micro Devices |
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43 / 346 page  Chapter 3 Software Environment 25 20695H/0—March 1998 AMD-K6® Processor Data Sheet Preliminary Information Figure 9. Segment Usage Instruction Pointer The instruction pointer (EIP or IP) is used in conjunction with the code segment register (CS). The instruction pointer is either a 32-bit register (EIP) or a 16-bit register (IP) that keeps track of where the next instruction resides within memory. This register cannot be directly manipulated, but can be altered by modifying return pointers when a JMP or CALL instruction is used. Floating-Point Registers The floating-point execution unit in the AMD-K6 processor is designed to perform mathematical operations on non-integer numbers. This floating-point unit conforms to the IEEE 754 and 854 standards and uses several registers to meet these standards — eight numeric floating-point registers, a status word register, a control word register, and a tag word register. Segment Register Real Mode Memory Model Segment Selector Physical Memory Protected Mode Memory Model Base Descriptor Table Physical Memory Segment Base Base Limit Base Limit Segment Base |
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