AM79C985JC datasheet(17/48 Pages) AMD

17 / 48 page

Am79C985

PRELIMINARY

Connection to Alternate Media

The eIMR+ device can be connected to the AUI port of

any MAU device. Thus, it can support 10BASE-2,

10BASE-5, and 10BASE-FL. To connect to an alternate

media type, on-chip ﬁltering should be disabled. This

can be achieved by substituting the normal 110-

Ω re-

sistor connected across the TXD differential output with

a 500-

Ω resistor. If on-chip ﬁltering is disabled at a TP

port, the Link Pulse must also be disabled. Refer to the

section on

eIMR+ Management Commands for pro-

gramming details.

Once port ﬁltering is disabled, the TXD output will be a

square waveform and can be connected to the AUI port

of a transceiver. Some external components are

nec-

essary to correctly interface the TXD output to the trans-

ceiver.

Twisted Pair Receivers

RXD is a differential twisted-pair receiver. When prop-

erly terminated, RXD will meet the electrical require-

ments for 10BASE-T receivers as speciﬁed in IEEE

802.3, Section 14.3.1.3. The receivers do not require

external ﬁlter modules. Proper termination is shown in

the

Systems Applications section.

The receiver’s threshold voltage can be programmed to

an extended-distance mode. In this mode, the differen-

tial receiver’s threshold is reduced to allow a longer

cable than the 100 meters speciﬁed in the IEEE 802.3

standard. For programming details, refer to the

Man-

agement Commands section.

Link Test

The integrated TP ports implement the Link Test func-

tion, as speciﬁed in the IEEE 802.3 10BASE-T stan-

dard. The eIMR+ device will transmit Link Test pulses

to any TP port after that port’s transmitter has been in-

active for more than 8 ms to 17 ms. Conversely, if a TP

port does not receive any data packets or Link Test

pulses for more than 65 ms to 132 ms and the Link Test

function is enabled for that port, then that port will enter

the link-fail state. The eIMR+ device will disable a port

in link-fail state (i.e., disable repeater transmit and re-

ceive functions) until it receives either four consecutive

Link Test pulses or a data packet.

The Link Test function can be disabled via the eIMR+

management port on a port-by-port basis, to allow the

eIMR+ device to operate with pre-10BASE-T networks

that do not implement the Link Test function. When the

Link Test function is disabled, the eIMR+ device will not

allow the TP port to enter link-fail state, even if no Link

Test pulses or data packets are being received. Note,

however, that the eIMR+ device will always transmit

Link Test pulses to all TP ports, regardless of whether

or not the port is enabled, partitioned, in link-fail state,

or has its Link Test function disabled. Separate man-

agement commands exist for enabling and disabling

the transmission of Link Test pulses on a port-by-port

basis.

Polarity Reversal

The TP ports can be programmed to receive data if a

wiring error results in a data packet being received at a

TP port with reversed polarity. This function will be en-

abled upon reception of a negative End Transmit Delim-

iter (ETD) or negative pulses and allows subsequent

packets to be received with the correct polarity. The po-

larity-reversal function is executed once following reset

or link-fail and can be programmed via the manage-

ment port to be enabled or disabled on a port-by-port

basis. The function may be enabled or disabled, follow-

ing a reset, depending on the level of the SI signal on

the rising edge of the RST pulse.

Visual Status Monitoring (LED) Support

The eIMR+ status port can be connected to LEDs to

facilitate the visual monitoring of repeater port status.

The status port has twelve output signals, LDA0-4, and

LDB0-4, LDGA, and LDGB. LDA0-4 and LDB0-4 repre-

sent the four TP ports and AUI port. LDGA and LDGB

are global indicators. Attributes that may be monitored

are Carrier Sense (CRS), Collision (COL), Partition

(PAR), Link Status (LINK), Loopback (LB), Port Dis-

abled (DIS), and Jabber (JAB). Three control bits,

LDC0-2, select the particular attributes to be displayed

on the LEDs. Table 1 shows how the programming

combinations for LDC0-2 control the attributes that will

be monitored.

Each LED drive pin (LDGA, LDGB, LDA0-4, and LDB0-4)

has two states: Off and LOW. When none of the se-

lected attributes are true, the driver is off and the diode

is unlit. When an attribute is true, the driver is LOW, and

the corresponding LEDs in Bank A or Bank B will be lit.

Some of the settings (LDC2 = 1) include a blink func-

tion. This allows two attributes to be selected for a given

state on the pin. As an example when LDC0-2 = 110,

the LDA outputs relating to TP ports will be solidly lit

when there is a link established at that port. However,

whenever there is activity on a port, the corresponding

LDA pin will switch on (LOW) and off at a period of 130

ms. Note that a partition on that port will also cause the

pin to go LOW.

On LDC settings that have two attributes for a state on

a pin (blink or solid-on), the attribute causing the output

to blink has priority. (Those attributes are shown in

Table 2 with a blink period speciﬁed next to it.) If an at-

tribute has no blink period speciﬁed, the LED indicates

the attribute by being solidly lit.

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