AM79C985JC datasheet(14/48 Pages) AMD

14 / 48 page

Am79C985

PRELIMINARY

LED Interface

LDA0-4, LDB0-4

LED Drivers

Output, Open Drain

LDA0-4 and LDB0-4 drive LED Bank A and LED Bank B,

respectively. LDA0 and LDB0 indicate the status of the

AUI port; LDA1-4 and LDB1-4 indicate the status of the

four TP ports. The port attributes monitored by LDA0-4

and LDB0-4 are programmed by three pins, LDC0-2.

LDGA

Global LED Driver, Bank A

Output, Open Drain

LDGA is the Global LED driver for LED Bank A. The

signal represents global CRS or COL conditions. In a

multiple-eIMR+ conﬁguration, LDGA from each of the

eIMR+ devices can be tied together to drive a single

global LED in Bank A.

LDGB

Global LED Driver, Bank B

Output, Open Drain

LDGB is the Global LED driver for LED Bank B. The

signal represents global CRS or JAB conditions. In a

multiple eIMR+ conﬁguration, LDGB from each of the

eIMR+ devices can be tied together to drive a single

global LED in Bank B.

LDC0-2

LED Control

Input

These pins select the attributes that will be displayed

on LDA0-4, LDB0-4, LDGA, and LDGB. If an LED is pro-

grammed to display two attributes, the attribute associ-

ated with the periodic blink takes precedence.

ACT0-7

Activity Display

Output, Open Drain

These signals drive the activity LEDs, which indicate

the percentage of network utilization. The display is up-

dated every 250 ms.

Miscellaneous Pins

RST

Reset

Input, Active LOW

When RST is LOW, the eIMR+ device resets to its de-

fault state. On the rising (trailing) edge of RST, the

eIMR+ also monitors the state of the SELI0-1, SI, and

AMODE pins, to conﬁgure the operating mode of the

device. In multiple eIMR+ systems, the falling (leading)

edge of the RST signal must be synchronized to CLK.

CLK

Master Clock In

Input

This pin is a 20-MHz clock input.

REXT

External Reference

Input

This pin is used for an internal current reference. It must

be tied to VDD via a 13-k

Ω resistor with 1% tolerance.

VDD

Power

Power Pin

This pin supplies power to the device.

AVSS

Analog Ground

Ground Pin

This pin is the ground reference for the differential

receivers and drivers.

DVSS

Digital Ground

Ground Pin

This pin is the ground reference for all the digital logic

in the eIMR+ device.

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