AM79C985 datasheet(29/48 Pages) AMD

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Am79C985

PRELIMINARY

Enable Software Override of Bank-B LEDs (Per Port -

AUI and TP, Global)

SI Data

1100 ####

SO Data (Pri)

None

SO Data (Sec)

None

This command forces the LEDs in Bank B to blink. In-

dividual LEDs and combinations of LEDs can be select-

ed via the lower four bits of the command byte, as

follows.

####

Port(s) affected

0000-0111 TP0 - TP7

1000

Primary AUI

1001

Secondary AUI

1010

Both AUI ports

1011

All TP ports

1100

All ports

1101

Primary Global

1110

Secondary Global

The designated LED drivers(s) will switch between

LOW and ‘off’ at the rate set by the Software Override

of LED Blink Rate command. Enable Software Override

of Bank B LEDs references the blink rate last issued,

and overrides any other attribute speciﬁed by LDC0-2.

Software override of LEDs is disabled after reset.

Software Override of LED Blink Rate

SI Data

1110 1###

SO Data (Pri)

None

SO Data (Sec)

None

This command sets the blink Period of the LEDs with

Software Override enabled. The duty cycle is 50%. This

command defaults to ‘off’ at reset.

Setting

Blink Period

1110 1000

Off

1110 1001

512 ms

1110 1010

1560 ms

1110 1011

Solid On

These settings apply to the blink rate for both Bank A

and Bank B. This command must precede the Enable

Software Override of Bank A/B LEDs command. All LED

combinations selected for software override will refer-

ence the blink rate last issued.

Get (Read Commands)

AUI Port(s) Status

SI Data

1000 1111

SO Data (Sec)

PBSLP PBSLS

SO Data (Pri)

0000 PBSL

SO Data (Single)

PBSL 0000

The combined AUI status of the eIMR+ device(s) allows

a single instruction to be used to monitor the AUI port(s).

The four local status bits are:

Partitioning Status

This bit is ‘0’ if the AUI port is partitioned and ‘1’ if the

AUI port is connected.

Bit Rate Error

This bit is set to ‘1’ if there is an instance of FIFO over-

ﬂow or underﬂow. The bit is cleared when the eIMR+

device is read.

SQE Test Status

This bit is set to ‘1’ if the SQE test error is detected by

the eIMR+ chip. The bit is cleared when the status is

read.

Loopback Error

The MAU attached to the AUI port is required to loop-

back data transmitted to DO onto the DI circuit. If the

loopback carrier is not detected by the eIMR+ device,

this bit is set to ‘1’. This bit is cleared when the status

is read.

If a single eIMR+ device is connected to a HIMIB device,

SO is PBSL 0000. If two eIMR+ devices are connected

to a HIMIB device, SO on the primary device is 0000

PBSLP, and SO on the secondary device is PBSLP

PBSLS. The subscript (P) indicates the statistics of the

primary eIMR+ device and the subscript (S) indicates

the statistics of the secondary eIMR+ device.

Alternate AUI Port(s) Status

There are three further variations of the AUI Port Status

Command allowing selective clearing of a combination

of B,S, and L bits. These are the following:

Alternate 1: B is not cleared, S and L are Cleared

SI Data

1000 1011

SO Data (Sec)

PBSLP PBSLS

SO Data (Pri)

0000 PBSL

SO Data (Single)

PBSL 0000

Alternate 2: S and L are not cleared, B is Cleared

SI Data

1000 1101

SO Data (Sec)

PBSLP PBSLS

SO Data (Pri)

0000 PBSL

SO Data (Single)

PBSL 0000

Alternate 3: None of S, B, and L are Cleared

SI Data

1000 1001

SO Data (Sec)

PBSLP PBSLS

SO Data (Pri)

0000 PBSL

SO Data (Single)

PBSL 0000

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