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AM79C985 датащи(PDF) 21 Page - Advanced Micro Devices |
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AM79C985 датащи(HTML) 21 Page - Advanced Micro Devices |
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21 / 48 page ![]() Am79C985 21 PRELIMINARY Figure 5. Internal Arbitration—eIMR+ Devices in Cascade Management Functions The eIMR+ device receives management commands in the form of byte-length data on the serial input pin, SI. If the eIMR+ device is expected to provide data in response to the command, it will send byte-length data to the serial-output pin, SO. Both the input and output data streams are clocked with the rising edge of the SCLK signal. The byte-length data is in RS232 serial- data format; that is, one start bit followed by eight data bits. The externally generated clock at the SCLK pin may be either a free-running clock synchronized to the input bit patterns, or a series of individual transitions meeting the setup-and-hold times with respect to the input bit pattern. If the latter method is used, 20 SCLK clock transitions are required for management com- mands that produce SO data, and 14 SCLK clock tran- sitions are required for management commands that do not produce SO data. VDD 1k Ω SELI_0 SELI_1 SELO SELI_0 SELI_1 SELO SELI_0 SELI_1 SELO SELI_0 SELI_1 SELO SELI_0 SELI_1 SELO SELI_0 SELI_1 SELO SELI_0 SELI_1 SELO 20651B-10 |
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