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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C976KCW датащи(PDF) 44 Page - Advanced Micro Devices |
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AM79C976KCW датащи(HTML) 44 Page - Advanced Micro Devices |
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44 / 309 page  44 Am79C976 8/01/00 P R E L I M INARY )LJXUH1RQ%XUVW:ULWH 7UDQVIHU %DVLF%XUVW:ULWH 7UDQVIHU The Am79C976 controller supports burst mode for all bus master write operations. To allow burst transfers in descriptor write operations, the Am79C976 controller must be programmed to use SWSTYLE 3, 4, or 5 (BCR20, bits 7-0). The controller uses the following rules to determine whether to use the PCI Memory Write (MW) command or the Memory Write and Invalidate (MWI) command for burst write transfers. — When a transfer starts on a cache line boundary, and there is at least a cache line of data to trans- fer, use MWI. — When a transfer does not start on a cache line boundary, use MW. (The external PCI bridge should stop the transfer at the cache line bound- ary if it can make good use of the MWI com- mand.) — Stop the MWI transfer at a cache line boundary if there is less than 1 cache line of data left to transfer. The Receive FIFO threshold should be greater than or equal to the cache line size to maximize the use of the MWI command. If the PCI bridge stops a transfer, the Am79C976 device waits until the FIFO threshold con- ditions are met before resuming the transfer. During the address phase of a burst write transfer AD[1:0] will both be 0 indicating a linear burst order. The byte enable signals indicate which byte lanes have valid data. The Am79C976 controller will always perform a single burst write transaction per bus mastership period, where transaction is defined as one address phase and one or multiple data phases. The Am79C976 controller supports zero wait state write cycles when using the Memory Write command. When using Memory Write and Invalidate commands, the device may insert IRDY wait states anywhere in the transaction. The device asserts IRDY immediately after the address phase and at the same time starts sampling DEVSEL. FRAME is deasserted when the next-to-last data phase is completed. Figure 14 shows a typical burst write access. The Am79C976 controller arbitrates for the bus, is granted access, and writes four 32-bit words (DWords) to the system memory and then releases the bus. In this ex- FRAME CLK AD IRDY TRDY C/BE DEVSEL REQ GNT PAR DEVSEL is sampled ADDR 0111 PAR 1 2345678 10 9 DATA ADDR DATA PAR PAR PAR BE 0111 BE 22929B15 |
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