AM79C976KCW datasheet(30/309 Pages) AMD

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Am79C976

8/01/00

P R E L I M INARY

RX_CLK

Receive Clock

Input

RX_CLK is a clock input that provides the timing refer-

ence for the transfer of the RX_DV, RXD[3:0], and

RX_ER signals into the Am79C976 device. RX_CLK

must provide a nibble rate clock (25% of the network

data rate). Hence, an MII transceiver operating at 10

Mbps must provide an RX_CLK frequency of 2.5 MHz

and an MII transceiver operating at 100 Mbps must pro-

vide an RX_CLK frequency of 25 MHz. When the exter-

nal PHY switches the RX_CLK and TX_CLK, it must

provide glitch-free clock pulses.

RXD[3:0]

Receive Data

Input

RXD[3:0] is the nibble-wide MII receive data bus. Data

on RXD[3:0] is sampled on every rising edge of

RX_CLK while RX_DV is asserted. RXD[3:0] is ignored

while RX_DV is de-asserted.

RX_DV

Receive Data Valid

Input

RX_DV is an input used to indicate that valid, received

data is being presented on the RXD[3:0] pins and

RX_CLK is synchronous to the receive data. In order

for a frame to be fully received by the Am79C976 de-

vice on the MII, RX_DV must be asserted prior to the

RX_CLK rising edge, when the first nibble of the Start-

of-Frame Delimiter is driven on RXD[3:0], and must re-

main asserted until after the rising edge of RX_CLK,

when the last nibble of the CRC is driven on RXD[3:0].

RX_DV must then be deasserted prior to the RX_CLK

rising edge which follows this final nibble. RX_DV tran-

sitions are synchronous to RX_CLK rising edges.

RX_ER

Receive Error

Input

RX_ER is an input that indicates that the MII trans-

ceiver device has detected a coding error in the receive

frame currently being transferred on the RXD[3:0] pins.

When RX_ER is asserted while RX_DV is asserted, a

CRC error will be indicated in the receive descriptor for

the incoming receive frame. RX_ER is ignored while

RX_DV is deasserted. Special code groups generated

on RXD while RX_DV is deasserted are ignored (e.g.,

Bad SSD in TX and IDLE in T4). RX_ER transitions are

synchronous to RX_CLK rising edges.

MDC

Management Data Clock

Output

MDC is a non-continuous clock output that provides a

timing reference for bits on the MDIO pin. During MII

management port operations, MDC runs at a nominal

frequency of 2.5 MHz. When no management opera-

tions are in progress, MDC is driven LOW.

If the MII Management port is not used, the MDC pin

can be left floating.

MDIO

Management Data I/O

Input/Output

MDIO is the bidirectional MII management port data

pin. MDIO is an output during the header portion of the

management frame transfers and during the data por-

tions of write transfers. MDIO is an input during the

data portions of read data transfers. When an operation

is not in progress on the management port, MDIO is not

driven. MDIO transitions from the Am79C976 controller

are synchronous to MDC falling edges.

If the PHY is attached through an MII physical connec-

tor, then the MDIO pin should be externally pulled down

to VSS with a 10-k

W ±5% resistor. If the PHY is perma-

nently connected, then the MDIO pin should be exter-

nally pulled up to VCC with a 10-k

W ±5% resistor.

External Address Detection Interface

EAR

External Address Reject

Input

The incoming frame will be checked against the inter-

nally active address detection mechanisms and the re-

sult of this check will be OR’d with the value on the EAR

pin. The EAR pin acts as an external address accept

function. The pin value is OR’d with the internal ad-

dress detection result to determine if the current frame

should be accepted. If EAR remains high while a frame

is being received, the frame will be accepted regard-

less of the state of the internal address matching logic.

The EAR pin must not be left unconnected. If it is not

used, it should be tied to VSS through a 10-k

W ±5% re-

sistor.

SFBD

Start Frame-Byte Delimiter

Output

An initial rising edge on the SFBD signal indicates that

a start of valid data is present on the RXD[3:0] pins.

SFBD will go high for one nibble time (400 ns when op-

erating at 10 Mbps and 40 ns when operating at 100

Mbps) one RX_CLK period after RX_DV has been as-

serted and RX_ER is deasserted, and there is the de-

tection of the SFD (Start of Frame Delimiter) of a

received frame.

Data on the RXD[3:0] will be the start of the destination

address field. SFBD will subsequently toggle every nib-

ble time (1.25 MHz frequency when operating at 10

Mbps and 12.5 MHz frequency when operating at 100

Mbps), indicating the first nibble of each subsequent

byte of the received nibble stream. The RX_CLK

should be used in conjunction with the SFBD to latch

the correct data for external address matching. SFBD

will be active only during frame reception.

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