AM79C976 datasheet(128/309 Pages) AMD

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Am79C976

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P R E L I M INARY

AUTOPOLL5: Auto-Poll5 Register

Offset 092h

This register controls the automatic polling of a user-

selectable external PHY register, AP_REG5.

All bits in this register are set to their default values by

H_RESET. All bits are also set to their default values

before EEPROM data are loaded or after an EEPROM

read failure.

The default value for all bits in this register is 0.

Table 37.

AUTOPOLL5: Auto-Poll5 Register

%$'55HFHLYH5LQJ%DVH $GGUHVV5HJLVWHU

Offset 120h

This 64-bit register allows the Receive Descriptor Ring

to be located anywhere in a 64-bit address space. For

systems with a 32-bit or smaller address space, it is

only necessary to program the lower 32 bits of this reg-

ister (by writing to offset 120h). The upper 32 bits will

remain at the default value of 0.

The contents of this register are set to the default value

0 when the RST pin is asserted. This register is not af-

fected by the serial EEPROM read operation or by a se-

rial EEPROM read error.

Table 38. Receive Ring Base Address Register

Bit

Name

Description

AP_REG5_EN

Enable Bit for Autopoll Register 5. When this bit and the Auto-Poll External PHY bit (APEP) in

CMD1 are both set to 1, the Auto-Poll State Machine periodically reads the external PHY register

selected by the AP_PHY5_ADDR and AP_REG5_ADDR fields and sets the APINT5 interrupt bit

if it detects a change in the register’s contents.

14-13

RES

Reserved locations. Written as zeros and read as undefined.

12-8

AP_REG5_ADDR

AP_REG5 Address. This field contains the register number of an external PHY register that the

Auto-Poll State Machine will periodically read if the AP_REG5_EN bit in this register and the

APEP bit (CMD3, bit 24) is set.

RES

Reserved location. Written as zero and read as undefined.

AP_PRE_SUP5

Auto-Poll Preamble Suppression. If this bit is set to 1, the Auto-Poll State Machine will suppress

the preambles of the MII Management Frames that it uses to periodically read the external PHY

This bit is ignored when the AP_PHY5_DFLT bit is set.

AP_PHY5_DFLT

Auto-Poll PHY5 Default. When this bit is set, the Auto-Poll State Machine ignores the contents of

the AP_PHY5_ADDR and AP_PRE_SUP5 fields and uses the AP_PHY0_ADDR field for the

address of the PHY device to be polled. If this bit is set, the Auto-Poll State Machine will suppress

preambles only if the Port Manager has determined that the default external PHY can accept MII

Management Frames without preambles. (The Port Manager examines bit 6 in register 1 of the

default PHY to make this determination.)

4-0

AP_PHY5_ADDR

Auto-Poll PHY5 Address. This field contains the address of the external PHY that contains

AP_REG5.

This bit is ignored when the AP_PHY5_DFLT bit is set.

Bit

Name

Description

63-0

BADR

Base Address of Receive Descriptor Ring. In systems with a 32-bit or smaller address space, it is

only necessary to program the 32 low-order bits of this register.

The low order 32 bits of this register are an alias of CSR24 and CSR25.

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