AM79C976 datasheet(108/309 Pages) AMD

108 / 309 page

108

Am79C976

8/01/00

P R E L I M INARY

:RUG,2 0RGH

After H_RESET, the Am79C976 controller is pro-

grammed to operate in Word I/O mode. DWIO (BCR18,

bit 7) will be cleared to 0. Table 22 shows how the 32

bytes of address space are used in Word I/O mode.

All I/O resources must be accessed in word quantities

and on word addresses. The Address PROM locations

can also be read in byte quantities. The only allowed

DWord operation is a write access to the RDP, which

switches the device to DWord I/O mode. A read access

other than those listed in Table 22 will yield undefined

data, and a write operation may cause unexpected re-

programming of the Am79C976 control registers.

Table 23 shows legal I/O accesses in Word I/O mode.

Note: * The offset of a MIB counter is the value con-

tained in the MIB Offset Register plus the offset shown

in Table 7 or Table 8.

'RXEOH:RUG ,20RGH

The Am79C976 controller can be configured to operate

in DWord (32-bit) I/O mode. The software can invoke

the DWIO mode by performing a DWord write access

to the I/O location at offset 10h (RDP). The data of the

write access must be such that it does not affect the in-

tended operation of the Am79C976 controller. Setting

the device into 32-bit I/O mode is usually the first oper-

ation after H_RESET or S_RESET. The RAP register

will point to CSR0 at that time. Writing a value of 0 to

CSR0 is a safe operation. DWIO (BCR18, bit 7) will be

set to 1 as an indication that the Am79C976 controller

operates in 32-bit I/O mode.

Note: Even though the I/O resource mapping changes

when the I/O mode setting changes, the RDP location

offset is the same for both modes. Once the DWIO bit

has been set to 1, only H_RESET can clear it to 0. The

DWIO mode setting is unaffected by S_RESET or set-

ting of the STOP bit. Table 24 shows how the 32 bytes

of address space are used in DWord I/O mode.

All I/O resources must be accessed in DWord quanti-

ties and on DWord addresses. A read access other

than listed in Table 25 will yield undefined data, and a

write operation may cause unexpected reprogramming

of the Am79C976 control registers.

DWIO mode applies to both I/O- and memory-mapped

accesses. Either a 32-bit I/O write to offset 10h relative

to the contents of the I/O Base Address Register (BAR)

or a 32-bit memory write to offset 10h relative to the

contents of the Memory BAR puts the device into

DWIO mode. Once in DWIO mode, the offsets of the

RAP, Reset, and BDP registers are 14h, 18h, and 1Ch

relative to the contents of either the I/O BAR or the

Memory BAR.

For example, in DWIO mode the BDP Register can be

read either by an I/O read from offset 1Ch relative to the

contents of the I/O BAR or by a memory read from off-

set 1Ch relative to the contents of the Memory BAR.

DWIO mode affects only the locations between 0 and

1Fh, which include the RAP, Reset, and BDP registers.

Registers at offset 20h and above are directly ac-

cessed in memory space by byte address and are un-

affected by DWIO.

The DWIO bit is also located at bit 28 of the CMD2 reg-

ister and can be set or cleared by software regardless

of its current setting.

Table 22. I/O Map In Word I/O Mode (DWIO = 0)

Offset

No. of

Bytes

00h - 0Fh

APROM

10h

RDP

12h

RAP (shared by RDP and BDP)

14h

Reset Register

16h

BDP

18h - 1Fh

Reserved

20h-1FFh

224

Memory-mapped Registers

256

MIB Counters

AM79C976 датащи(PDF) 108 Page - Advanced Micro Devices

AM79C976 датащи(HTML) 108 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL