AM79C976 datasheet(106/309 Pages) AMD

106 / 309 page

106

Am79C976

8/01/00

P R E L I M INARY

Software Access

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The Am79C976 controller implements the 256-byte

configuration space as defined by the PCI specification

revision 2.1. The 64-byte header includes all registers

required to identify the Am79C976 controller and its

function. Additionally, the optional PCI Power Manage-

ment Interface registers are implemented at location

44h - 4Bh. The layout of the Am79C976 PCI configura-

tion space is shown in Table 20.

The PCI configuration registers are accessible only by

configuration cycles. All multi-byte numeric fields follow

Little Endian byte ordering. All write accesses to Re-

served locations have no effect; reads from these loca-

tions will return a data value of 0.

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The Am79C976 controller requires 4K bytes of memory

address space for access to all the various internal reg-

isters as well as access to some setup information

stored in an external serial EEPROM. For compatibility

with previous PCnet family devices, the lower 32 bytes

of the register space are also mapped into I/O space,

but some functions of the Am79C976 controller (such

as network statistics) are only available in memory

space.

The Am79C976 controller supports mapping the ad-

dress space to both I/O and memory space. The value

in the PCI I/O Base Address register determines the

start address of the I/O address space. The register is

typically programmed by the PCI configuration utility

after system power-up. The PCI configuration utility

must also set the IOEN bit in the PCI Command register

to enable I/O accesses to the Am79C976 controller.

For memory mapped I/O access, the PCI Memory

Mapped I/O Base Address register controls the start

Table 20.

PCI Configuration Space Layout

Offset

Device ID

Vendor ID

00h

Status

Command

04h

Base-Class

Sub-Class

Programming IF

Revision ID

08h

Reserved

Header Type

Latency Timer

Cache Line Size

0Ch

I/O Base Address

10h

Memory-Mapped I/O Base Address

14h

Reserved

18h

Reserved

1Ch

Reserved

20h

Reserved

24h

Reserved

28h

Subsystem ID

Subsystem Vendor ID

2Ch

Expansion ROM Base Address

30h

Reserved

CAP-PTR

34h

Reserved

38h

MAX_LAT

MIN_GNT

Interrupt Pin

Interrupt Line

3Ch

Reserved

40h

PMC

NXT_ITM_PTR

CAP_ID

44h

DATA_REG

PMCSR_BSE

PMCSR

48h

Reserved

FCh

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