AM79C976 datasheet(112/309 Pages) AMD

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112

Am79C976

8/01/00

P R E L I M INARY

The PCI Command register is read and written by the

host.

Bit

Name

Description

15-10

RES

Reserved locations. Read as ze-

ros; write operations have no ef-

fect.

FBTBEN

Fast Back-to-Back Enable. When

this bit is set to 1, the Am79C976

controller

will

generate

Fast

Back-to-Back cycles. When this

bit is cleared to 0, the Am79C976

controller will not generate Fast

Back-to-Back cycles.

FBTBEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

SERREN

SERR Enable. Controls the as-

sertion of the SERR pin. SERR is

disabled

when

SERREN

cleared. SERR will be asserted

on detection of an address parity

error and if both SERREN and

PERREN (bit 6 of this register)

are set.

SERREN

cleared

H_RESET and is not effected by

S_RESET or by setting the STOP

bit.

RES

Reserved location. Read as ze-

ros; write operations have no ef-

fect.

PERREN

Parity Error Response Enable.

Enables the parity error response

functions. When PERREN is 0

and the Am79C976 controller de-

tects a parity error, it only sets the

Detected Parity Error bit in the

PCI Status register. When PER-

REN is 1, the Am79C976 control-

ler

asserts

PERR

the

detection of a data parity error. It

also sets the DATAPERR bit (PCI

Status register, bit 8), when the

data parity error occurred during

a master cycle. PERREN also

enables reporting address parity

errors through the SERR pin and

the SERR bit in the PCI Status

PERREN

cleared

H_RESET and is not affected by

S_RESET or by setting the STOP

bit.

VGASNOOP

VGA Palette Snoop. Read as ze-

ro; write operations have no ef-

fect.

MWIEN

Memory Write and Invalidate Cy-

cle Enable. When this bit is set to

1, the Am79C976 controller will

generate Memory Write and In-

validate (MWI) cycles when ap-

propriate. When the bit is cleared

to 0, the device will generate

Memory Write cycles instead of

MWI cycles.

MWIEN is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

SCYCEN

Special Cycle Enable. Read as

zero; write operations have no ef-

fect. The Am79C976 controller

ignores all Special Cycle opera-

tions.

BMEN

Bus

Master

Enable.

Setting

BMEN enables the Am79C976

controller to become a bus mas-

ter on the PCI bus. The host must

set BMEN before setting the INIT

or STRT bit in CSR0 of the

Am79C976 controller.

BMEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

MEMEN

Memory Space Access Enable.

The Am79C976 controller will ig-

nore all memory accesses when

MEMEN is cleared. The host

must set MEMEN before the first

memory access to the device.

For memory mapped I/O, the

host must program the PCI Mem-

ory Mapped I/O Base Address

dress before setting MEMEN.

For accesses to the Expansion

ROM, the host must program the

PCI Expansion ROM Base Ad-

dress register at offset 30h with a

valid memory address before set-

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