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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C976 датащи(PDF) 103 Page - Advanced Micro Devices |
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AM79C976 датащи(HTML) 103 Page - Advanced Micro Devices |
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103 / 309 page  8/01/00 Am79C976 103 P R E L I M INARY )LJXUH 3DWWHUQ0DWFK5$0 IEEE 1149.1 (1990) Test Access Port Interface An IEEE 1149.1-compatible boundary scan Test Ac- cess Port is provided for board-level continuity test and diagnostics. All digital input, output, and input/output pins are tested. The following paragraphs summarize the IEEE 1149.1-compatible test functions imple- mented in the Am79C976 controller. %RXQGDU\ 6FDQ&LUFXLW The boundary scan test circuit requires four pins (TCK, TMS, TDI and TDO), defined as the Test Access Port (TAP). It includes a finite state machine (FSM), an in- struction register, a data register array. Internal pull-up resistors are provided for the TDI, TCK, and TMS pins. 7$3)LQLWH 6WDWH 0DFKLQH The TAP engine is a 16-state finite state machine (FSM), driven by the Test Clock (TCK), and the Test Mode Select (TMS) pins. The FSM is reset when TMS and TDI are high for five TCK periods. 6XSSRUWHG,QVWUXFWLRQV In addition to the minimum IEEE 1149.1 requirements (BYPASS, EXTEST, and SAMPLE instructions), three additional instructions (IDCODE, TRIBYP, and SET- BYP) are provided to further ease board-level testing. All unused instruction codes are reserved. See Table 17 for a summary of supported instructions. BCR Bit Number BCR 47 BCR 46 BCR45 15 8 7 0 15 8 7 0 15 8 PMAT1 PMAT0 15 8 7 0 31 24 23 16 15 8 PMR_B4 PMR_B3 PMR_B2 PMR_B1 PMR_B0 Pattern Match RAM Address Pattern Match RAM Bit Number 39 32 31 24 23 16 15 8 7 0 Comments 0 P3 pointer P2 pointer P1 pointer P0 pointer Pattern Enable bits First Address 1 P7 pointer P6 pointer P5 pointer P4 pointer X Second Address 2 Data Byte 3 Data Byte 2 Data Byte1 Data Byte 0 Pattern Control Start Pattern P1 2+n Data Byte 4n+3 Date Byte 4n+2 Data Byte 4n+1 Data Byte 4n+0 Pattern Control End Pattern P1 J Data Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 Pattern Control Start Pattern Pk J+m Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m+1 Data Byte 4m+0 Pattern Control End Pattern Pk 7 6 5 4 3 2 1 0 EOP SKIP MASK |
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