AM79C971VCW datasheet(181/265 Pages) AMD

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Am79C971

181

P R E L I M INARY

RLEN and TLEN

When SSIZE32 (BCR20, bit 8) is set to 0, the software

structures are defined to be 16 bits wide, and the RLEN

and TLEN fields in the initialization block are each three

bits wide. The values in these fields determine the

number of transmit and receive Descriptor Ring Entries

(DRE) which are used in the descriptor rings. Their

meaning is shown in Table 44. If a value other than

those listed in Table 44 is desired, CSR76 and CSR78

can be written after initialization is complete.

When SSIZE32 (BCR20, bit 8) is set to 1, the software

structures are defined to be 32 bits wide, and the RLEN

and TLEN fields in the initialization block are each 4

bits wide. The values in these fields determine the

number of transmit and receive Descriptor Ring Entries

(DRE) which are used in the descriptor rings. Their

meaning is shown in Table 45.

If a value other than those listed in Table 45 is desired,

CSR76 and CSR78 can be written after initialization is

complete.

RDRA and TDRA

RDRA and TDRA indicate where the transmit and re-

ceive descriptor rings begin. Each DRE must be lo-

cated at a 16-byte address boundary when SSIZE32 is

set to 1 (BCR20, bit 8). Each DRE must be located at

an 8-byte address boundary when SSIZE32 is set to 0

(BCR20, bit 8).

Table 42.

Initialization Block (SSIZE32 = 0)

Address

Bits 15-13

Bit 12

Bits 11-8

Bits 7-4

Bits 3-0

IADR+00h

MODE 15-00

IADR+02h

PADR 15-00

IADR+04h

PADR 31-16

IADR+06h

PADR 47-32

IADR+08h

LADRF 15-00

IADR+0Ah

LADRF 31-16

IADR+0Ch

LADRF 47-32

IADR+0Eh

LADRF 63-48

IADR+10h

RDRA 15-00

IADR+12h

RLEN

RES

RDRA 23-16

IADR+14h

TDRA 15-00

IADR+16h

TLEN

RES

TDRA 23-16

Table 43.

Initialization Block (SSIZE32 = 1)

Address

Bits

31-28

27-24

23-20

19-16

15-12

11-8

7-4

3-0

IADR+00h

TLEN

RES

RLEN

RES

MODE

IADR+04h

PADR 31-00

IADR+08h

RES

PADR 47-32

IADR+0Ch

LADRF 31-00

IADR+10h

LADRF 63-32

IADR+14h

RDRA 31-00

IADR+18h

TDRA 31-00

Table 44.

R/TLEN Decoding (SSIZE32 = 0)

R/TLEN

Number of DREs

000

001

010

011

100

101

110

111

128

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