AM79C971VCW datasheet(182/265 Pages) AMD

182 / 265 page

182

Am79C971

P R E L I M INARY

LADRF

The Logical Address Filter (LADRF) is a 64-bit mask

that is used to accept incoming Logical Addresses. If

the first bit in the incoming address (as transmitted on

the wire) is a 1, it indicates a logical address. If the first

bit is a 0, it is a physical address and is compared

against the physical address that was loaded through

the initialization block.

A logical address is passed through the CRC genera-

tor, producing a 32-bit result. The high order 6 bits of

the CRC is used to select one of the 64 bit positions in

the Logical Address Filter. If the selected filter bit is set,

the address is accepted and the frame is placed into

memory.

The Logical Address Filter is used in multicast address-

ing schemes. The acceptance of the incoming frame

based on the filter value indicates that the message

may be intended for the node. It is the node’s responsi-

bility to determine if the message is actually intended

for the node by comparing the destination address of

the stored message with a list of acceptable logical ad-

dresses.

If the Logical Address Filter is loaded with all zeros and

promiscuous mode is disabled, all incoming logical ad-

dresses except broadcast will be rejected. See Figure

57.

Figure 57.

Address Match Logic

PADR

This 48-bit value represents the unique node address

assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and

used for internal address comparison. PADR[0] is com-

pared with the first bit in the destination address of the

incoming frame. It must be 0 since only the destination

address of a unicast frames is compared to PADR. The

six hex-digit nomenclature used by the ISO 8802-3

(IEEE/ANSI 802.3) maps to the Am79C971 PADR reg-

ister as follows: the first byte is compared with

PADR[7:0], with PADR[0] being the least significant bit

of the byte. The second ISO 8802-3 (IEEE/ANSI 802.3)

byte is compared with PADR[15:8], again from the least

significant bit to the most significant bit, and so on. The

sixth byte is compared with PADR[47:40], the least sig-

nificant bit being PADR[40].

Table 45.

R/TLEN Decoding (SSIZE32 = 1)

R/TLEN

Number of DREs

0000

0001

0010

0011

0100

0101

0110

0111

128

1000

256

1001

512

11XX

512

1X1X

512

CRC

GEN

SEL

MUX

Match = 1 Packet Accepted

Match = 0 Packet Rejected

Match

Logical

Address Filter

(LADRF)

32-Bit Resultant CRC

Received Message

Destination Address

20550D-60

AM79C971VCW датащи(PDF) 182 Page - Advanced Micro Devices

AM79C971VCW датащи(HTML) 182 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL