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AM79C971VCW датащи(PDF) 210 Page - Advanced Micro Devices

номер детали AM79C971VCW
подробное описание детали  PCnet??FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
PDF  265 Pages
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производитель  AMD [Advanced Micro Devices]
домашняя страница  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C971VCW датащи(HTML) 210 Page - Advanced Micro Devices

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Am79C971
SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS DETECTION INTERFACE
Note:
1. May need to delay RX_CLK to capture Start Frame Byte Delimiter (SFBD) at 100 Mbps operation.
Parameter
Symbol
Parameter Name
Test Condition
Min
Max
Unit
External Address Detection Interface: Internal PHY
tEAD1
SRD setup to
↑ SRDCLK
40
ns
tEAD2
SRD hold to
↑ SRDCLK
40
ns
tEAD3
SFBD# change to
↓ SRDCLK
-15
+15
ns
tEAD4
EAR deassertion to
↑ SRDCLK (first
rising edge)
50
ns
tEAD5
EAR assertion after SFD event
(frame rejection)
0
51,090
ns
tEAD6
EAR assertion width
110
ns
External Address Detection Interface: External PHY - MII @ 25 MHz
tEAD7
SFBD change from
↓ RX_CLK
0
20 (Note 1) ns
tEAD8
EAR deassertion to
↑ RX_CLK (first
rising edge)
40
ns
tEAD9
EAR assertion after SFD event
(frame rejection)
0
5,080
ns
tEAD10
EAR assertion width
50
ns
External Address Detection Interface: External PHY - MII @ 2.5 MHz
tEAD11
EAR deassertion to
↑ RX_CLK (first
rising edge)
400
ns
tEAD12
EAR assertion after SFD event
(frame rejection)
0
50,800
ns
tEAD13
EAR assertion width
500
ns
Receive Frame Tag Timing with Media Independent Interface
tEAD14
RXFRTGE assertion from
↑SFBD
(first rising edge)
0
ns
tEAD15
RXFRTGE, RXFRTGD setup to
↑
RX_CLK
10
ns
tEAD16
RXFRTGE, RXFRTGD hold to
↑
RX_CLK
10
ns
tEAD17
RXFRTGE deassertion to
↓ RX_DV
RX_CLK @25 MHz
RX_CLK @2.5 MHz
40
400
ns
ns



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