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AM79C971VCW датащи(PDF) 209 Page - Advanced Micro Devices

номер детали AM79C971VCW
подробное описание детали  PCnet??FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
PDF  265 Pages
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производитель  AMD [Advanced Micro Devices]
домашняя страница  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C971VCW датащи(HTML) 209 Page - Advanced Micro Devices

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Am79C971
209
SWITCHING CHARACTERISTICS: GENERAL-PURPOSE SERIAL INTERFACE
Notes:
1. CLSN must be asserted for a continuous period of 110 ns or more. Assertion for less than 110 ns period may or may not result
in CLSN recognition.
2. RXCLK should meet jitter requirements of IEEE 802.3 specification.
3. CLSN assertion before 51.2
µs will be indicated as a normal collision. CLSN assertion after 51.2 µs will be considered as a
Late Receive Collision.
Parameter
Symbol
Parameter Name
Test Condition
Min
Max
Unit
Transmit Timing
tGPT1
TXCLK Period (802.3 compliant)
@ 1.5 V
99.99
100.01
ns
tGPT2
TXCLK HIGH Time
@ 2.0 V
40
60
ns
tGPT3
TXDAT and TXEN Delay from
↑
TXCLK
@ 1.5 V
0
70
ns
tGPT4
RXEN Setup before
↑ TXCLK (Last
Bit)
@ 1.5 V
210
ns
tGPT5
RXEN Hold after
↓ TXEN
@ 1.5 V
0
ns
tGPT6
CLSN Active Time to Trigger
Collision
@ 1.5 V (Note 1)
410
ns
tGPT7
CLSN Active to
↓ RXEN to Prevent
LCAR Assertion
@ 1.5 V
0
ns
tGPT8
CLSN Active to
↓ RXEN for SQE
Heartbeat window
@ 1.5 V
0
4.0
µs
tGPT9
CLSN Active to
↑ RXEN for Normal
Collision
@ 1.5 V
0
51.2
µs
Receive Timing
tGPR1
RXCLK Period
@ 1.5 V (Note 2)
80
120
ns
tGPR2
RXCLK HIGH Time
@ 2.0 V (Note 2)
30
80
ns
tGPR3
RXCLK LOW Time
@ 0.8 V (Note 2)
30
80
ns
tGPR4
RXDAT and RXEN Setup to
↑
RXCLK
@ 1.5 V
15
ns
tGPR5
RXDAT Hold after
↑ RXCLK
@ 1.5 V
15
ns
tGPR6
RXEN Hold after
↓ RXCLK
@ 1.5 V
0
ns
tGPR7
CLSN Active to First
↑ RXCLK
(Collision Recognition)
@ 1.5 V
0
ns
tGPR8
CLSN Active to
↑ RXCLK for
Address Type Designation Bit
@ 1.5 V (Note 3)
51.2
µs
tGPR9
CLSN Setup to Last
↑ RXCLK for
Collision Recognition
@ 1.5 V
210
ns
tGPR10
CLSN Active
@ 1.5 V
410
ns
tGPR11
CLSN Inactive Setup to First
↑
RXCLK
@ 1.5 V
300
ns
tGPR12
CLSN Inactive Hold to Last
↑ RXCLK @ 1.5 V
300
ns



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