AM53CF96 datasheet(16/76 Pages) AMD

16 / 76 page

P R E L I M I N A R Y

AMD

Am53CF94/Am53CF96

RSTC

Reset Control

(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. The Reset SCSI

command will cause the device to drive

RSTC active for

25 ms–40 ms, which will depend on the CLK frequency

and the conversion factor. When the device is config-

ured in the Single Ended SCSI Mode (

DFMODE inac-

tive) this pin is defined as a

RST output for the SCSI bus.

When the device is configured in the Differential SCSI

Mode (

DFMODE active) this pin is defined as the direc-

tion control for the external differential transceiver. In

this mode, a signal high state corresponds to an output

to the SCSI bus and a low state corresponds to an input

from the SCSI bus.

REQC

Request Control

(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. This signal is

activated only in the Target mode.

ACKC

Acknowledge Control

(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. This signal is ac-

tivated only in the Initiator mode.

ISEL

Initiator Select

(Output, Active High)

This signal is available on the Am53CF96 only. This sig-

nal is active whenever the device is in the Initiator mode.

In the differential mode this signal is used to enable the

Initiator signals

ACKC and ATN and the device also

drives these signals.

TSEL

Target Select

(Output, Active High)

This signal is available on the Am53CF96 only. This sig-

nal is active whenever the device is in the Target mode.

In the differential mode this signal is used to enable the

Target signals

REQC, MSG, C/D and I/O and the device

also drives these signals.

FUNCTIONAL DESCRIPTION

Address

(Hex.)

Operation

Read

Current Transfer Count

Write

Start Transfer Count Register

Low

Read

Current Transfer Count

Write

Start Transfer Count Register

Middle

Read/Write

FIFO Register

Read/Write

Command Register

Read

Status Register

Write

SCSI Destination ID Register

Read

Interrupt Status Register

Write

SCSI Timeout Register

Read

Internal State Register

Write

Synchronous Transfer Period

Address

(Hex.)

Operation

Read

Current FIFO/Internal State

Write

Synchronous Offset Register

Read/Write

Control Register 1

Write

Clock Factor Register

Write

Forced Test Mode Register

Read/Write

Control Register 2

Read/Write

Control Register 3

Read/Write

Control Register 4

Read

Current Transfer Count

Write

Start Transfer Count

Write

Data Alignment Register

Note:

Not all registers in this device are both readable and writable. Some read only registers share the same address with write only

registers. The registers can be accessed by asserting the

CS signal and then asserting either RD or WR signal depending on the

operation to be performed. Only the FIFO Register can be accessed by asserting either

CS or DACK in conjunction with RD and

WR signals or DMARD and DMAWR signals. The register address inputs are ignored when DACK is used but must be valid

when

CS is used.

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