AM53CF96 datasheet(31/76 Pages) AMD

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P R E L I M I N A R Y

AMD

Am53CF94/Am53CF96

Forced Test Mode Register (0AH) Write

Forced Test Mode Register

FTMREG

Address: 0AH

Type: Write

7654

210

RES

FHI

FIM

FTM

xxxxx

Reserved

Forced High Impedance Mode

Forced Initiator Mode

Forced Target Mode

Reserved

17348B-30

The Forced Test Mode Register (FTMREG) is for test

use only. The STE bit in the Control Register One

(CNTLREG1) must be set for the FTMREG to operate.

FTMREG – Bits 7:3 – RES – Reserved

FTMREG – Bit 2 – FHI – Forced High Impedance

Mode

The FHI bit when set places all the output and bidirec-

tional pins into a high impedance state. It is zeroed by a

hardware or chip reset.

FTMREG – Bit 1 – FIM – Forced Initiator Mode

The FIM bit when set forces the ESC into the Initiator

mode. As an Initiator, the device will drive SCSI data

lines, and

ACK or ATN (depending on the bus phase and

the command loaded in the Command Register). The

ESC will remain in this mode for as long as

BSY is as-

serted, or until a Reset SCSI Bus or Reset Device com-

mand occurs. During normal operation this bit must not

be set.

FTMREG – Bit 0 – FTM – Forced Target Mode

The FTM bit when set forces the ESC into the Target

mode. As a Target, the device does not assert

BSY;

rather, it drives SCSI data lines,

REQ, MSG, C/D or I/O

(depending on the command loaded in the Command

connect Steps, Reset SCSI Bus, or Reset Device com-

mand occurs. During normal operation this bit must not

be set.

Control Register Two (0BH) Read/Write

Data Alignment Enable

Control Register Two

CNTLREG2

Address: 0BH

Type: Read/Write

76543

210

DAE

ENF

SBO

TSDR

S2FE

ACDPE

PGRP

PGDP

0000

000

Enable Features

Select Byte Order

Tri-State DMA Request

SCSI-2 Features Enable

Abort on Command/Data Parity Error

Pass Through/Generate Register Parity

Pass Through/Generate Data Parity

17348B-31

The Control Register Two (CNTLREG2) sets up the de-

vice with various operating parameters.

CNTLREG2 – Bit 7 – DAE – Data Alignment Enable

The DAE bit is used in the Initiator Synchronous Data-In

phase only. When the DAE bit is set one byte is reserved

at the bottom of the FIFO when the phase changes to

the Synchronous Data-In phase. The contents of this

byte will become the lower byte of the DMA word (16-bit)

transferred to the memory, the upper byte being the first

byte of the first word received from the SCSI bus.

Note:

If an interrupt is received for a misaligned boundary on a

phase change to synchronous data the following recov-

ery procedure may be followed. The host processor

should copy the byte at the start address in the host

memory to the Data Alignment Register 0FH (DALREG)

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