AD7713 datasheet(23/28 Pages) AD

23 / 28 page

REV. D

AD7713

–23–

Table V shows some typical 8XC51 code used for a single 24-bit

read from the output register of the AD7713. Table V shows

some typical code for a single write operation to the control

write operation while the AD7713 expects the MSB first, so the

data to be transmitted has to be rearranged before being written

to the output serial register. Similarly, the AD7713 outputs the

MSB first during a read operation while the 8XC51 expects the

LSB first. Therefore, the data which is read into the serial buffer

needs to be rearranged before the correct data-word from the

AD7713 is available in the accumulator.

Table V. 8XC51 Code for Reading from the AD7713

MOV SCON,#00010001B;

Configure 8051 for MODE 0

MOV IE,#00010000B;

Disable All Interrupts

SETB 90H;

Set P1.0, Used as

RFS

SETB 91H;

Set P1.1, Used as

TFS

SETB 93H;

Set P1.3, Used as A0

MOV R1,#003H;

Sets Number of Bytes to Be Read

in A Read Operation

MOV R0,#030H;

Start Address for Where Bytes

Will Be Loaded

MOV R6,#004H;

Use P1.2 as

DRDY

WAIT:

NOP;

MOV A,P1;

Read Port 1

ANL A,R6;

Mask Out All Bits Except

DRDY

JZ READ;

If Zero Read

SJMP WAIT;

Otherwise Keep Polling

READ:

CLR 90H;

Bring

RFS Low

CLR 98H;

Clear Receive Flag

POLL:

JB 98H, READ1

Tests Receive Interrupt Flag

SJMP POLL

READ 1:

MOV A,SBUF;

Read Buffer

RLC A;

Rearrange Data

MOV B.0,C;

Reverse Order of Bits

RLC A; MOV B.1,C; RLC A; MOV B.2,C;

RLC A; MOV B.3,C; RLC A; MOV B.4,C;

RLC A; MOV B.5,C; RLC A; MOV B.6,C;

RLC A; MOV B.7,C;

MOV A,B;

MOV @R0,A;

Write Data to Memory

INC R0;

Increment Memory Location

DEC R1

Decrement Byte Counter

MOV A,R1

JZ END

Jump if Zero

JMP WAIT

Fetch Next Byte

END:

SETB 90H

Bring

RFS High

FIN:

SJMP FIN

Table VI. 8XC51 Code for Writing to the AD7713

MOV SCON,#00000000B;

Configure 8051 for MODE 0

Operation and Enable Serial

Reception

MOV IE,#10010000B;

Enable Transmit Interrupt

MOV IP,#00010000B;

Prioritize the Transmit Interrupt

SETB 91H;

Bring

TFS High

SETB 90H;

Bring

RFS High

MOV R1,#003H;

Sets Number of Bytes to Be

Written in a Write Operation

MOV R0,#030H;

Start Address in RAM for Bytes

MOV A,#00H;

Clear Accumulator

MOV SBUF,A;

Initialize the Serial Port

WAIT:

JMP WAIT;

Wait for Interrupt

INT ROUTINE:

NOP;

Interrupt Subroutine

MOV A,R1;

Load R1 to Accumulator

JZ FIN;

If Zero Jump to FIN

DEC R1;

Decrement R1 Byte Counter

MOV A,@R;

Move Byte into the Accumulator

INC R0;

Increment Address

RLC A;

Rearrange Data—From LSB

First to MSB First

MOV B.0,C; RLC A; MOV B.1,C; RLC A;

MOV B.2,C; RLC A; MOV B.3,C; RLC A;

MOV B.4,C; RLC A; MOV B.5,C; RLC A;

MOV B.6,C; RLC A: MOV B.7,C; MOV A,B;

CLR 93H;

Bring A0 Low

CLR 91H;

Bring

TFS Low

MOV SBUF,A;

Write to Serial Port

RETI;

Return from Subroutine

FIN:

SETB 91H;

Set

TFS High

SETB 93H;

Set A0 High

RETI;

Return from Interrupt Subroutine

AD7713 to 68HC11 Interface

Figure 18 shows an interface between the AD7713 and the

68HC11 microcontroller. The AD7713 is configured for its exter-

nal clocking mode, while the SPI port is used on the 68HC11,

which is in its single chip mode. The

DRDY line from the AD7713

is connected to the Port PC2 input of the 68HC11, so the

DRDY

line is polled by the 68HC11. The

DRDY line can be connected to

the IRQ input of the 68HC11 if an interrupt driven system is

preferred. The 68HC11 MOSI and MISO lines should be config-

ured for wired-OR operation. Depending on the interface

configuration, it may be necessary to provide bidirectional buffers

between the 68HC11 MOSI and MISO lines.

The 68HC11 is configured in the master mode with its CPOL

bit set to a Logic 0 and its CPHA bit set to a Logic 1.

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