MP9181 – 3A, 4.5V-20V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)

MP9181 Rev 1.01

www.MonolithicPower.com

11

12/10/2012

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© 2012 MPS. All Rights Reserved.

To realize the stability when no external ramp is

used, usually the ESR value should be chosen

as follow:

SW

ON

ESR

OUT

TT

0.7

2

R

C

+

×π

≥

(4)

Ramp with small ESR Cap

When the output capacitors are ceramic ones,

the ESR ripple is not high enough to stabilize the

system, and external ramp compensation is

needed. Skip to application information section

for design steps with small ESR caps

.

R1

R2

Ceramic

SW

FB

Vo

L

R4

C4

R9

Figure 8—Simplified Circuit in PWM Mode

with External Ramp Compensation

Figure 8 shows a simplified external ramp

compensation (R4 and C4) for PWM mode, with

HS-FET off. Chose R1, R2, R9 and C4 of the

external ramp to meet the following condition:

12

9

SW

4

1

2

RR

11

R

2F

C

5

R

R

⎛⎞

×

<×

+

⎜⎟

π×

×

+

⎝⎠

(5)

where:

R4

C4

FB

C4

II

I

I

=+

≈

(6)

then be estimated as:

IN

OUT

12

RAMP

ON

44

1

2

9

VV

R//R

VT

RC

R // R

R

−

=×

×

×+

(7)

follows

−

−

==

×

OUT

RAMP

SLOPE1

off

4

4

V

V

V

TR

C

(8)

As can be seen from equation 8, if there is

instability in PWM mode, we can reduce either

R4 or C4. If C4 can not be reduced further due to

limitation from equation 5, then we can only

reduce R4. For a stable PWM operation, the

SW

ON

-3

ESR

OUT

slope1

OUT

OUT

SW

on

TT

+-R

C

Io 10

0.7 π

2

-V

V

+

2L C

T -T

×

×

≥

××

(9)

Io is the load current.

ripple is the same whether the external ramp is

used or not. Figure9 shows the simplified circuit

of the skip mode when both the HS-FET and LS-

FET are off.

R1

R2

ESR

Cout

FB

Vo

Ro

Figure 9—Simplified Circuit in skip Mode

mode can be determined as follow:

()

REF

SLOPE2

12

OUT

V

V

(R

R //Ro) C

−

=

+×

(10)

where Ro is the equivalent load resistor.

is lower than that is in the PWM mode, so it is

reasonable that the jitter in the skip mode is

larger. If one wants a system with less jitter

resistors should not be too big, however, that will

decrease the light load efficiency.

When using a large-ESR capacitor on, the output,

add a ceramic capacitor with a value of 10uF or

less to in parallel to minimize the effect of ESL.