MP8352 – 3V to 6V INPUT, 6A, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER

MP8352 Rev. 1.0

www.MonolithicPower.com

10

1/25/2010

MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.

© 2010 MPS. All Rights Reserved.

The input capacitor can be electrolytic, tantalum

or ceramic. When using electrolytic or tantalum

capacitors, a small, high quality ceramic

capacitor, i.e. 0.1µF, should be placed as close

to the IC as possible. When using ceramic

capacitors, make sure that they have enough

capacitance to provide sufficient charge to

prevent excessive voltage ripple at input. The

input voltage ripple caused by capacitance can

be estimated by:

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

×

×

×

=

∆

IN

OUT

IN

OUT

S

LOAD

IN

V

V

1

V

V

1

C

f

I

V

Selecting the Output Capacitor

The output capacitor (C2) is required to

maintain the DC output voltage. Ceramic,

tantalum, or low ESR electrolytic capacitors are

recommended.

Low

ESR

capacitors

are

preferred to keep the output voltage ripple low.

The output voltage ripple can be estimated by:

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

×

×

+

×

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

×

×

=

∆

2

C

f

8

1

R

V

V

1

L

f

V

V

S

ESR

IN

OUT

S

OUT

OUT

equivalent series resistance (ESR) value of the

output capacitor.

In the case of ceramic capacitors, the

impedance at the switching frequency is

dominated by the capacitance. The output

voltage ripple is mainly caused by the

capacitance. For simplification, the output

voltage ripple can be estimated by:

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

×

×

×

×

=

IN

OUT

2

S

OUT

OUT

V

V

1

2

C

L

f

8

V

∆V

In the case of tantalum or electrolytic capacitors,

the ESR dominates the impedance at the

switching frequency. For simplification, the

output ripple can be approximated to:

ESR

IN

OUT

S

OUT

OUT

R

V

V

1

L

f

V

∆V

×

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

×

×

=

The characteristics of the output capacitor also

affect the stability of the regulation system. The

MP8352 can be optimized for a wide range of

capacitance and ESR values.

PCB Layout Guide

PCB layout is very important to achieve stable

operation. It is highly recommended to duplicate

EVB layout for optimum performance.

If change is necessary, please follow these

guidelines and take Figure 3 for references.

1) Keep the path of switching current short

and minimize the loop area formed by Input

cap, high-side MOSFET and low-side

MOSFET/schottky diode (as the red dotted

line loop shows).

2) Keep

the

connection

of

low-side

MOSFET/schottky diode between SW pin

and input power ground as short and wide

as possible.

3) Bypass ceramic capacitors are suggested

4) Ensure all feedback connections are short

and direct. Place the feedback resistors

and compensation components as close to

the chip as possible.

5) Route SW away from sensitive analog

areas such as FB.

6) Connect IN, SW, and especially GND

respectively to a large copper area to cool

the chip to improve thermal performance

and long-term reliability.

BG

VCC

BST

SW

GND

FB

N/C

VOUT

PGND

Single Point

Connection

External Blas Supply

SGND

L

PG

IN

IN

IN

SW

SW

EN/SYNC

Only Top Layer Shown,

and a Ground Plane Is Assumed