AD9224ARSZ datasheet(18/24 Pages) AD

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AD9224

–18–

REV. A

DIGITAL INPUTS AND OUTPUTS

Digital Outputs

The AD9224 output data is presented in positive true straight

binary for all input ranges. Table IV indicates the output data

formats for various input ranges regardless of the selected input

range. A twos complement output data format can be created

by inverting the MSB.

Table IV. Output Data Format

Input (V)

Condition (V)

Digital Output

OTR

VINA–VINB

< – VREF

0000 0000 0000

VINA–VINB

= – VREF

0000 0000 0000

VINA–VINB

= 0

1000 0000 0000

VINA–VINB

= + VREF – 1 LSB

1111 1111 1111

VINA–VINB

≥ + VREF

1111 1111 1111

1111 1111 1110

OTR

–FS

+FS

–FS+1/2 LSB

+FS –1/2 LSB

–FS –1/2 LSB

+FS –1 1/2 LSB

0000 0000 0001

0000 0000 0000

OTR DATA OUTPUTS

Figure 31. Output Data Format

Out of Range (OTR)

An out-of-range condition exists when the analog input voltage

is beyond the input range of the converter. OTR is a digital out-

put that is updated along with the data output corresponding to

the particular sampled analog input voltage. Hence, OTR has

the same pipeline delay (latency) as the digital data. It is LOW

when the analog input voltage is within the analog input range.

It is HIGH when the analog input voltage exceeds the input

range as shown in Figure 31. OTR will remain HIGH until the

analog input returns within the input range and another conver-

sion is completed. By logical ANDing OTR with the MSB

and its complement, overrange high or underrange low con-

ditions can be detected. Table V is a truth table for the over/

underrange circuit in Figure 32 which uses NAND gates. Sys-

tems requiring programmable gain conditioning of the AD9224

input signal can immediately detect an out-of-range condition,

thus eliminating gain selection iterations. Also, OTR can be

used for digital offset and gain calibration.

Table V. Out-of-Range Truth Table

OTR

MSB

Analog Input Is

In Range

Underrange

Overrange

OVER = “1”

UNDER = “1”

MSB

OTR

MSB

Figure 32. Overrange or Underrange Logic

Digital Output Driver Considerations (DRVDD)

The AD9224 output drivers can be configured to interface with

+5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V

respectively. The output drivers are sized to provide sufficient

output current to drive a wide variety of logic families. However,

large drive currents tend to cause glitches on the supplies and

may affect SINAD performance. Applications requiring the

ADC to drive large capacitive loads or large fanout may require

additional decoupling capacitors on DRVDD. In extreme cases,

external buffers or latches may be required.

Clock Input and Considerations

The AD9224 internal timing uses the two edges of the clock

input to generate a variety of internal timing signals. The clock

input must meet or exceed the minimum specified pulse width

high and low (tCH and tCL) specifications for the given A/D as

defined in the Switching Specifications at the beginning of the

data sheet to meet the rated performance specifications. For

example, the clock input to the AD9224 operating at 40 MSPS

may have a duty cycle between 49% to 51% to meet this timing

requirement since the minimum specified tCH and tCL is 12.37 ns.

For low clock rates below 40 MSPS, the duty cycle may deviate

from this range to the extent that both tCH and tCL are satisfied.

High speed high resolution A/Ds are sensitive to the quality of

the clock input. The degradation in SNR at a given full-scale

input frequency (fIN) due only to aperture jitter (tA) can be cal-

culated with the following equation:

SNR = 20 log10 [1/2

π f

IN tA]

In the equation, the rms aperture jitter, tA, represents the root-

sum square of all the jitter sources, which include the clock in-

put, analog input signal, and A/D aperture jitter specification.

Undersampling applications are particularly sensitive to jitter.

Clock input should be treated as an analog signal in cases where

aperture jitter may affect the dynamic range of the AD9224.

Power supplies for clock drivers should be separated from the

A/D output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter crystal controlled oscillators make

the best clock sources. If the clock is generated from another

type of source (by gating, dividing or other method), it should

be retimed by the original clock at the last step.

The clock input is referred to the analog supply. Its logic thresh-

old is AVDD/2. If the clock is being generated by 3 V logic, it

will have to be level shifted into 5 V CMOS logic levels. This

can also be accomplished by ac-coupling and level-shifting the

clock signal.

The AD9224 has a very tight clock tolerance at 40 MHz. One

way to minimize the tolerance of a 50% duty cycle clock is to

divide down a clock of higher frequency, as shown in Figure 33.

+5V

80MHz

40MHz

Figure 33. Divide-by-Two Clock Circuit

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