AD7274 datasheet(18/28 Pages) AD

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AD7273/AD7274

Rev. 0 | Page 17 of 28

MODES OF OPERATION

The mode of operation of the AD7273/AD7274 is selected by

controlling the logic state of the CS signal during a conversion.

There are three possible modes of operation: normal mode,

partial power-down mode, and full power-down mode. The

point at which CS is pulled high after the conversion is initiated

determines which power-down mode, if any, the device enters.

Similarly, if the device is already in power-down mode, CS can

control whether the device returns to normal operation or

remains in power-down mode. These modes of operation are

designed to provide flexible power management options, which

can be chosen to optimize the power dissipation/throughput

rate ratio for different application requirements.

NORMAL MODE

This mode is intended for fastest throughput rate performance

because the AD7273/AD7274 remain fully powered at all times,

eliminating worry about power-up times. Figure 29 shows the

general diagram of the operation of the AD7273/AD7274 in

this mode.

The conversion is initiated on the falling edge of CS as described

in the Serial Interface section. To ensure that the part remains

fully powered up at all times, CS must remain low until at least

10 SCLK falling edges elapse after the falling edge of CS. If CS is

brought high any time after the 10th SCLK falling, but before the

16th SCLK falling edge, the part remains powered up, but the

conversion is terminated, and SDATA goes back into three-state.

For the AD7274, a minimum of 14 serial clock cycles are

required to complete the conversion and access the complete

conversion result. For the AD7273, a minimum of 12 serial

clock cycles are required to complete the conversion and access

the complete conversion result.

CS can idle high until the next conversion or low until CS

returns high before the next conversion (effectively idling CS

low). Once a data transfer is complete (SDATA has returned to

three-state), another conversion can be initiated after the quiet

time, tQUIET, has elapsed by bringing CS low again.

PARTIAL POWER-DOWN MODE

This mode is intended for use in applications where slower

throughput rates are required. An example of this is when either

the ADC is powered down between each conversion or a series

of conversions is performed at a high throughput rate and then

the ADC is powered down for a relatively long duration between

these bursts of several conversions.

When the AD7273/AD7274 are in partial power-down mode,

all analog circuitry is powered down except the bias generation

circuit.

To enter partial power-down mode, interrupt the conversion

process by bringing CS high between the second and 10th falling

edges of SCLK, as shown in Figure 30. Once CS is brought high

in this window of SCLKs, the part enters partial power-down

mode, the conversion that was initiated by the falling edge of

CS is terminated, and SDATA goes back into three-state. If CS

is brought high before the second SCLK falling edge, the part

remains in normal mode and does not power down. This prevents

accidental power-down due to glitches on the CS line.

To exit this mode of operation and power up the AD7274/

AD7273, perform a dummy conversion. On the falling edge of

CS, the device begins to power up and continues to power up as

long as CS is held low until after the falling edge of the 10th SCLK.

The device is fully powered up once 16 SCLKs elapse; valid data

results from the next conversion, as shown in Figure 31. If CS is

brought high before the 10th falling edge of SCLK, the AD7274/

AD7273 goes into full power-down mode. Therefore, although

the device may begin to power up on the falling edge of CS, it

powers down on the rising edge of CS as long as this occurs

before the 10th SCLK falling edge.

If the AD7273/AD7274 is already in partial power-down mode

and CS is brought high before the 10th falling edges of SCLK, the

device enters full power-down mode. For more information on

the power-up times associated with partial power-down mode

in various configurations, see the Power-Up Times section.

FULL POWER-DOWN MODE

This mode is intended for use in applications where throughput

rates slower than those in the partial power-down mode are

required, because power-up from a full power-down takes

substantially longer than that from a partial power-down. This

mode is suited to applications where a series of conversions

performed at a relatively high throughput rate are followed by

a long period of inactivity and thus power-down.

When the AD7273/AD7274 are in full power-down mode, all

analog circuitry is powered down. To enter full power-down

mode put the device into partial power-down mode by bringing

CS high between the second and 10

th falling edges of SCLK. In

the next conversion cycle, interrupt the conversion process in

the way shown in Figure 32 by bringing CS high before the 10

SCLK falling edge. Once CS is brought high in this window of

SCLKs, the part powers down completely. Note that it is not

necessary to complete 16 SCLKs once CS is brought high to enter

either of the power-down modes. Glitch protection is not

available when entering full power-down mode.

To exit full power-down mode and power up the AD7273/

AD7274 again, perform a dummy conversion, similar to when

powering up from partial power-down mode. On the falling

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