AD7274 datasheet(16/28 Pages) AD

16 / 28 page

AD7273/AD7274

Rev. 0 | Page 15 of 28

CIRCUIT INFORMATION

The AD7273/AD7274 are high speed, low power, 10-/12-bit,

single supply ADCs, respectively. The parts can be operated

from a 2.35 V to 3.6 V supply. When operated from any supply

voltage within this range, the AD7273/AD7274 are capable of

throughput rates of 3 MSPS when provided with a 48 MHz clock.

The AD7273/AD7274 provide the user with an on-chip track-

and-hold ADC and a serial interface housed in an 8-lead TSOT

or an 8-lead MSOP package, which offers the user considerable

space-saving advantages over alternative solutions. The serial

clock input accesses data from the part and provides the clock

source for the successive approximation ADC. The analog input

range is 0 to VREF. An external reference in the range of 1.4 V to

VDD is required by the ADC.

The AD7273/AD7274 also feature a power-down option to save

power between conversions. The power-down feature is

implemented across the standard serial interface as described in

the Modes of Operation section.

CONVERTER OPERATION

The AD7273/AD7274 are successive approximation ADCs

based on a charge redistribution DAC. Figure 24 and Figure 25

show simplified schematics of the ADC. Figure 24 shows the

ADC during its acquisition phase, where SW2 is closed, SW1 is

in Position A, the comparator is held in a balanced condition,

and the sampling capacitor acquires the signal on VIN.

COMPARATOR

ACQUISITION

PHASE

VDD/2

SW2

VIN

SAMPLING

CAPACITOR

AGND

SW1

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

Figure 24. ADC Acquisition Phase

When the ADC starts a conversion, SW2 opens and SW1 moves

to Position B, causing the comparator to become unbalanced

(see Figure 25). The control logic and the charge redistribution

DAC are used to add and subtract fixed amounts of charge from

the sampling capacitor to bring the comparator back into a

balanced condition. When the comparator is rebalanced, the

conversion is complete. The control logic generates the ADC

output code. Figure 26 shows the ADC transfer function.

COMPARATOR

ACQUISITION

PHASE

VDD/2

SW2

VIN

SAMPLING

CAPACITOR

AGND

SW1

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

Figure 25. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding of the AD7273/AD7274 is straight binary.

The designed code transitions occur midway between

successive integer LSB values, such as 0.5 LSB and 1.5 LSB. The

LSB size is VREF/4,096 for the AD7274 and VREF/1,024 for the

AD7273. The ideal transfer characteristic for the

AD7273/AD7274 is shown in Figure 26.

000...000

ANALOG INPUT

111...111

000...001

111...000

011...111

111...110

000...010

1LSB = VREF/4096 (AD7274)

1LSB = VREF/1024 (AD7273)

+VREF – 1.5LSB

0.5LSB

Figure 26. AD7273/AD7274 Transfer Characteristic

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