REV. B

AD7865

–14–

Using an External Clock

With the

H/S SEL and INT/EXT CLK pins tied to Logic 1, the

AD7865 will expect to be driven from an external clock. The

highest external clock frequency allowed is 5 MHz. This means

a conversion time of 3.2

µs compared to 2.4 µs using the inter-

nal clock. In some instances, however, it may be useful to use an

external clock when high throughput rates are not required. For

example, two or more AD7865s may be synchronized by using

the same external clock for all devices. In this way there is no

latency between output logic signals like

EOC due to differences

in the frequency of the internal clock oscillators. Figure 10

shows how the various logic outputs are synchronized to the CLK

signal. The first falling edge of CLKIN must not occur until

200 ns after a conversion has been initiated (rising edge of

CONVST), at which point BUSY will go high. The AD7865

will then convert the analog input signal on the first selected

channel (see Selecting a Conversion Sequence) at a rate deter-

mined by the CLKIN. No external events will occur until the

14th falling edge of CLKIN. The data register output address

is then reset to point to Data Register 1 and FRSTDATA goes

high. This first conversion is complete on the 15th falling edge

of the CLKIN (indicated by

EOC going low) and the result

from this conversion is loaded into Data Register 1.

EOC goes

high again on the 16th falling edge of CLKIN. Figure 10 shows

a

RD pulse occurring when EOC is low, enabling the conversion

result in Data Register 1 onto the data bus. The next 16 pulses

of CLKIN will convert the analog input signal on the second

selected channel and so on until all selected channels have been

converted. BUSY and

EOC will go low on the 15th falling edge

of the last conversion sequence and

EOC will return high on the

16th falling edge.

Standby Mode Operation

The AD7865 has a Standby Mode whereby the device can be

placed in a low current consumption mode (3

µA typ). The

AD7865 is placed in standby by bringing the logic input

STBY

low. The AD7865 can be powered up again for normal opera-

tion by bringing

STBY logic high. The output data buffers are

still operational while the AD7865 is in standby. This means the

user can still continue to access the conversion results while the

AD7865 is in standby. This feature can be used to reduce the

average power consumption in a system using low throughput

rates. To reduce the average power consumption the AD7865 can

be placed in standby at the end of each conversion sequence,

i.e., when BUSY goes low and taken out of standby again prior

to the start of the next conversion sequence. The time it takes

the AD7865 to come out of standby is called the “wake-up”

time. This wake-up time will limit the maximum throughput

rate at which the AD7865 can be operated when powering down

between conversions. The AD7865 will wake up in less than

1

µs when using an external reference. When the internal refer-

ence is used, the wake-up time depends on the amount of time

the AD7865 spends in standby mode. For standby times of less

than 10 ms the AD7865 will wake up in less than 5

µs (see Fig-

ure 11). For standby times greater than this some or all of the

charge on the external reference capacitor will have leaked away

and the wake-up time will be dependent on how long it takes to

recharge. For standby times less than one second the wake-up

time will be less than 1 ms. Even if the charge has been completely

depleted the wake-up time will typically be less than 10 ms.

STANDBY TIME –

s

0

0

2500

5000

7500

10000

2.5

5

Figure 11. Wake-Up Time vs. Standby Time Using the On-

Chip Reference

FIRST CONVERSION

COMPLETE

BUSY

RD

EOC

FRSTDATA

CONVST

CLK

2 34567 89 10 11 12 13 14 15 16 1

23456789 10 11 12 13 14

1

15 16

16

15

LAST CONVERSION

COMPLETE

Figure 10. Using an External Clock