REV. B

AD7865

–12–

TIMING AND CONTROL

Reading Between Each Conversion in the Conversion Sequence

Figure 7 shows the timing and control sequence required to

obtain the optimum throughput rate from the AD7865. To

obtain the optimum throughput from the AD7865 the user must

read the result of each conversion as it becomes available. The

timing diagram in Figure 7 shows a read operation each time the

EOC signal goes logic low. The timing in Figure 7 shows a

conversion on all four analog channels (SL1 to SL4 = 1, see

Selecting a Conversion Sequence), hence there are four

EOC

pulses and four read operations to access the result of each of

the four conversions.

A conversion is initiated on the rising edge of

CONVST. This

places all four track/holds into hold simultaneously. New data

from this conversion sequence is available for the first channel

µs later. The conversion on each subsequent

channel is completed at 2.4

µs intervals. The end of each con-

version is indicated by the falling edge of the

EOC signal. The

BUSY output signal indicates the end of conversion for all

selected channels (four in this case).

Data is read from the part via a 14-bit parallel data bus with

standard

CS and RD signals. The CS and RD inputs are inter-

nally gated to enable the conversion result onto the data bus.

The data lines DB0 to DB13 leave their high impedance state

when both

CS and RD are logic low. Therefore, CS may be

permanently tied logic low and the

RD signal used to access the

conversion result. Since each conversion result is latched into its

output data register at the same time

EOC goes logic low a

further option would be to tie the

EOC and RD pins together

with

CS tied logic low and use the rising edge of EOC to latch

the conversion result. Although the AD7865 has some special

features that permit reading during a conversion (e.g., a sepa-

performance it is recommended that the read operation be

completed when

EOC is logic low, i.e., before the start of the

next conversion. Although Figure 7 shows the read operation

taking place during the

EOC pulse, a read operation can take

place at any time. Figure 7 shows a timing specification called

“Quiet Time.” This is the amount of time that should be left

after a read operation and before the next conversion is initi-

ated. The quiet time heavily depends on data bus capacitance

but a figure of 50 ns to 150 ns is typical.

The signal labeled FRSTDATA (First Data Word) indicates to

the user that the pointer associated with the output data regis-

ters is pointing to the first conversion result by going logic high.

The pointer is reset to point to the first data location (i.e., first

conversion result,) at the end of the first conversion just prior to

EOC going low. The pointer is incremented to point to the next

register (next conversion result) by a rising edge of

RD only if

that conversion result is available. If a read takes place before

the next conversion is complete (as shown in Figure 7) then the

pointer is incremented at the end of that conversion when the

EOC pulse goes low. Hence, FRSTDATA in Figure 7 is seen to

go low just after to the second

EOC pulse. Repeated read

operations during a conversion will continue to access the data

at the current pointer location until the pointer is incremented

at the end of that conversion. Note: FRSTDATA has an indeter-

minate logic state after initial power-up. This means that for the

first conversion sequence after power-up, the FRSTDATA

logic output may already be logic high before the end of the first

conversion. This condition is indicated by the dashed line in

Figure 7. Also the FRSTDATA logic output may already be

high as a result of the previous read sequence as is the case after

the fourth read in Figure 7. The fourth read (rising edge of

RD)

resets the pointer to the first data location. There, however,

FRSTDATA is already high when the next conversion sequence

is initiated.

QUIET

TIME

100ns

100ns

DATA

CONVST

BUSY

EOC

FRSTDATA

RD

CS

H/S SEL

SL1–SL4

Figure 7. Timing Diagram for Reading During Conversion