LTC1702A datasheet(14/24 Pages) LINER

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LT3844

3844fb

APPLICATIONS INFORMATION

it advisable to further derate the capacitor or to choose a

capacitor rated at a higher temperature than required.

The combination of aluminum electrolytic capacitors and

ceramic capacitors is an economical approach to meet-

ing the input capacitor requirements. The capacitor volt-

age rating must be rated greater than VIN(MAX). Multiple

capacitors may also be paralleled to meet size or height

requirements in the design. Locate the capacitor very close

to the MOSFET switch and use short, wide PCB traces to

minimize parasitic inductance.

Step-Down Converter: Output Capacitor Selection

The output capacitance, COUT, selection is based on the

design’s output voltage ripple,

ΔVOUT and transient load

requirements.

ΔVOUT is a function of ΔIL and the COUT

ESR. It is calculated by:

Δ= Δ

⎛

⎝⎜

⎞

⎠⎟

ESR

OUT

•

(•

•

)

The maximum ESR required to meet a

ΔVOUT design

requirement can be calculated by:

ESR MAX

VL f

OUT

IN MAX

()

()( )(

)

•–

()

⎛⎛

⎝

⎜

⎞

⎠

⎟

Worst-case

ΔVOUT occurs at highest input voltage. Use

paralleled multiple capacitors to meet the ESR require-

ments. Increasing the inductance is an option to lower

the ESR requirements. For extremely low

ΔVOUT, an ad-

ditional LC ﬁlter stage can be added to the output of the

supply. Application Note 44 has some good tips on sizing

an additional output ﬁlter.

Output Voltage Programming

A resistive divider sets the DC output voltage according

to the following formula:

OUT

1 231

⎛

⎝⎜

⎞

⎠⎟

–

The external resistor divider is connected to the output

of the converter as shown in Figure 2. Tolerance of the

feedback resistors will add additional error to the output

voltage.

Example: VOUT = 12V; R1 = 10k

kuse

210

1 231

8748

866 1

=−

⎛

⎝⎜

⎞

⎠⎟

=−

The VFB pin input bias current is typically 25nA, so use

of extremely high value feedback resistors could cause a

converter output that is slightly higher than expected. Bias

current error at the output can be estimated as:

ΔVOUT(BIAS) = 25nA • R2

Supply UVLO and Shutdown

The SHDN pin has a precision voltage threshold with

hysteresis which can be used as an undervoltage lockout

threshold (UVLO) for the power supply. Undervoltage

lockout keeps the LT3844 in shutdown until the supply

input voltage is above a certain voltage programmed by

the user. The hysteresis voltage prevents noise from falsely

tripping UVLO.

Resistors are chosen by ﬁrst selecting RB. Then:

SUPPLY ON

⎛

⎝⎜

⎞

⎠⎟

•

–

()

135

VFB PIN

VOUT

COUT

3844 F02

SHDN PIN

VSUPPLY

3844 F03

Figure 2. Output Voltage Feedback Divider

Figure 3. Undervoltage Lockout Circuit

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