LNBH26 datasheet(12/38 Pages) STMICROELECTRONICS

12 / 38 page

Pin configuration

LNBH26

12/38

Doc ID 022771 Rev 1

Pin configuration

Figure 5.

Pin connections (top view)

AM10476v1

GND

DSQOUT -A

DSQIN -B

DSQIN -A

VUP -A

VCC

PGND

FLT

LX -B

LX -A

SDA

ISEL

DETIN -B

VUP -B

DETIN -A

VOUT -B

VOUT -A

DSQOUT -B

BYP

BPSW -A

ADDR

BPSW -B

SCL

Table 2.

Pin description

Symbol

Name

Pin function

DSQOUT-B

DiSEqC output

Open drain output of channel A tone detector to the main microcontroller

for DiSEqC 2.0 data decoding. It is low when tone is detected on the

DETIN-B input pin. Set to ground if not used.

2FLT

FLT

Open drain output for IC fault conditions. It is set low in case of overload

(OLF bit) or overheating status (OTF bit) or power not good (PNG bit) is

detected. To be connected to pull-up resistor (5 V max.).

LX-A

N-Mos drain

Channel A, integrated N-channel Power MOSFET drain.

P-GND

Power ground

DC-DC converter power ground. To be connected directly to the exposed

pad.

LX-B

N-Mos drain

Channel B, integrated N-channel Power MOSFET drain.

ADDR

Address setting

Two I2C bus addresses available by setting the address pin level voltage.

See

Table 16.

SCL

Serial clock

Clock from I²C bus.

SDA

Serial data

Bi-directional data from/to I²C bus.

ISEL

Current selection

for both channel

A and B

The resistor “RSEL” connected between ISEL and GND defines the linear

regulator current limit threshold. Refer to

Section 2.5. Also see the ISET

bit description in

Table 9. The RSEL resistor defines the same current

limit both for channels A and B.

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