PCF8576DTSLASHS400SLASH2 datasheet(36/57 Pages) NXP

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PCF8576D

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Product data sheet

Rev. 14 — 10 June 2013

36 of 57

NXP Semiconductors

PCF8576D

Universal LCD driver for low multiplex rates

13. Application information

13.1 Cascaded operation

In large display configurations, up to 16 PCF8576Ds can be differentiated on the same

I2C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the

programmable I2C-bus slave address (SA0).

PCF8576Ds connected in cascade are synchronized to allow the backplane signals from

only one device in the cascade to be shared. This arrangement is cost-effective in large

LCD applications since the backplane outputs of only one device need to be

through-plated to the backplane electrodes of the display. The other cascaded

PCF8576Ds contribute additional segment outputs but their backplane outputs are left

open-circuit (see Figure 23).

All PCF8576Ds connected in cascade are correctly synchronized by the SYNC signal.

This synchronization is guaranteed after the power-on reset. The only time that SYNC is

likely to be needed is if synchronization is lost accidentally, for example, by noise in

adverse electrical environments, or if the LCD multiplex drive mode is changed in an

application using several cascaded PCF8576Ds, as the drive mode cannot be changed

on all of the cascaded devices simultaneously. SYNC can be either an input or an output

signal; a SYNC output is implemented as an open-drain driver with an internal pull-up

resistor. The PCF8576D asserts SYNC at the start of its last active backplane signal and

monitors the SYNC line at all other times. If cascade synchronization is lost, it is restored

by the first PCF8576D to assert SYNC. The timing relationship between the backplane

waveforms and the SYNC signal for each LCD drive mode is shown in Figure 24.

Table 21.

Addressing cascaded PCF8576D

Cluster

Bit SA0

Pin A2

Pin A1

Pin A0

Device

100

000

011

102

113

004

015

106

117

210

008

019

1010

1111

0012

0113

1014

1115

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