12

11

2

VDD

AGND

SYNC

TPS53321

UDG-10207

1

8

EN

PS

4

3

VBST

PGD

10

FB

L1

1 mH

9

COMP

15

PGND

16

PGND

13

VIN

14

VIN

6

7

5

SW SW SW

EN_Master

C8

1 mF

R6

2.2 W

C6

0.1 mF

V

IN

3.3 V

C2 2.2 nF

R4

4.02 kW

C3

100 pF

C1

2.2 nF

R3

20 W

PGD_Master

C4

0.1 mF

V

IN

Output all MLCCs

C5

22 mF

C

OUT

3 x 22 mF

R1

4.02 kW

R2

4.02 kW

R7

20 kW

V

12

11

2

VDD

AGND

SYNC

TPS53321

1

8

EN

PS

4

3

VBST

PGD

10

FB

L11

1 mH

9

COMP

15

PGND

16

PGND

13

VIN

14

VIN

6

7

5

SW SW SW

EN_Slave

C18

1 mF

R16

2.2 W

C16

0.1 mF

C12 2.2 nF

R14

4.02 kW

C13

100 pF

C11

2.2 nF

R13

20 W

PGD_Master

C14

0.1 mF

V

IN

Output all MLCCs

C15

22 mF

C

OUT

3 x 22 mF

R11

4.02 kW

R12

2.67 kW

R17

20 kW

V

V

IN

TPS53321

www.ti.com

SLUSAF3 – DECEMBER 2010

Figure 17 shows the master/slave configuration schematic for a design with a 3.3-V input.

Figure 17. Master/Slave Configuration Schematic

Copyright © 2010, Texas Instruments Incorporated

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