TPS53321

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SLUSAF3 – DECEMBER 2010

Another set of overcurrent circuitry monitors the current flowing through low-side FET. If the current through the

low-side FET exceeds 6.8 A, the overcurrent protection is enabled and immediately turns off both the high-side

and the low-side FETs and shuts down the converter. The device is fully protected against overcurrent during

both on-time and off-time. The device attempts to restart after a hiccup delay of 14.5 ms (typical). If the

overcurrent condition clears before restart, the device starts up normally.

Overvoltage Protection

The TPS53321 monitors the voltage divided feedback voltage to detect overvoltage and undervoltage conditions.

When the feedback voltage is greater than 117% of the reference, the high-side MOSFET turns off and the

low-side MOSFET turns on. The output voltage then drops until it reaches the undervoltage threshold. At that

point the low-side MOSFET turns off and the device enters a high-impedance state.

Undervoltage Protection

When the feedback voltage is lower than 83% of the reference voltage, the undervoltage protection timer starts.

If the feedback voltage remains lower than the undervoltage threshold voltage after 10 ms, the device turns off

both the high-side and the low-side MOSFETs and goes into a high-impedance state. The device attempts to

restart after a hiccup delay of 14.5 ms (typical).

Overtemperature Protection

The TPS53321 continuously monitors the die temperature. If the die temperature exceeds the threshold value

(140

˚C typical), the device shuts off. When the device temperature falls to 40˚C below the overtemperature

threshold, it restarts and returns to normal operation.

Output Discharge

When the enable pin is low, the TPS53321 discharges the output capacitors through an internal MOSFET switch

between SW and PGND while high-side and low-side MOSFETs remain off. The typical discharge switch-on

resistance is 60

Master/Slave Operation and Synchronization

Two TPS53321 can operate interleaved when configured as master/slave. The SYNC pins of the two devices are

connected together for synchronization. In CCM, the master device sends the 180° out-of-phase pulse to the

slave device through the SYNC pin, which determines the leading edge of the PWM pulse. If the slave device

does not receive the SYNC pulse from the master device or if the SYNC connection is broken during operation,

the slave device continues to operate using its own internal clock.

In DE mode, the master/slave switching node does not synchronize to each other if either one of them is

operating in DCM. When both master and slave enter CCM, the switching nodes of the master and the slave

synchronize to each other.

The SYNC pin of the slave device can also connect to external clock source within ±20% of the 1.1-MHz

switching frequency. The falling edge of the SYNC triggers the rising edge of the PWM signal.

Copyright © 2010, Texas Instruments Incorporated

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