LTC4305CDHD datasheet(12/20 Pages) LINER

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LTC4305

4305f

disconnects the downstream buses from the upstream

bus by de-biasing the Upstream-Downstream Buffers.

Note that the downstream switches remain in their exist-

ing state. The Timeout Real Time bit of register 0 indicates

the real-time status of the stuck low situation. The Latched

Timeout Bit of register 0 is a latched bit that is set high

when a timeout occurs.

External Faults on the Downstream Channels

When a slave on downstream channel 1 pulls the ALERT1

pin below 1V, the LTC4305 passes this information to

master on the upstream bus by pulling the ALERT pin low.

The functionality is the same for the slaves on down-

stream channel 2 and the ALERT2 pin. Each channel has

its own dedicated fault bit in Register 0, so that masters

can read Register 0 to determine which channels have

faults.

ALERT Functionality and Fault Resolution

When a fault occurs, the LTC4305 pulls the ALERT pin low,

as described previously. The procedure for resolving

faults depends on the type of fault. If a master on the

upstream bus is communicating with devices on a down-

stream bus via the upstream-downstream buffer circuitry—

channel 1, for example—and a device on this bus pulls the

ALERT1 pin low, the LTC4305 acts transparently, and the

master communicates directly with the device that caused

the fault via the Upstream-Downstream Buffer circuitry to

resolve the fault.

In all other cases, the LTC4305 communicates with the

master to resolve the fault. After the master broadcasts the

Alert Response Address (ARA), the LTC4305 will respond

with its address on the SDAIN line and release the ALERT

pin. The ALERT line will also be released if the LTC4305 is

addressed by the master.

The ALERT signal will not be pulled low again until a

different type of fault has occurred or the original fault is

cleared and has occurred again. Figure 2 shows the details

of how the fault latches and ALERT pin are set and reset.

The Downstream Bus Connection Fault and faults that

occur on unconnected downstream buses are grouped

together and generate a single signal to drive ALERT. The

Stuck Low Timeout Fault has its own dedicated pathway to

ALERT; however, once a stuck low occurs, another one

will not occur until the first one is cleared. For these

reasons, once the master has established the LTC4305 as

the source of the fault, it should read register 0 to deter-

mine the specific problem, take action to solve the prob-

lem, and clear the fault promptly. All faults are cleared by

writing a dummy databyte to register 0, which is a read-

only register.

For example, assume that a fault occurs, the master sends

out the ARA, and the LTC4305 successfully writes

its address onto SDAIN and releases its ALERT pin. The

master reads register 0 and learns that the ALERT2 logic

state bit is low. The master now knows that a device on

downstream bus 2 has a fault and writes to register 3 to

connect to bus 2, so that it can communicate with the

source of the fault. At this point, the master writes to

I2C Device Addressing

Twenty-seven distinct bus addresses are configurable

using the three state ADR0, ADR1 and ADR2 pins. Table

1 shows the correspondence between pin states and

addresses. Note that address bits a6 and a5 are internally

configured to 1 and 0, respectively. In addition, the

LTC4305 responds to two special addresses. Address

(1011 110) is a mass write used to write all LTC4305’s,

OPERATIO

Figure 2. Setting and Resetting the ALERT Pin

4305 F02

VCC

WRITE

FAULT ON CONNECTED

DOWNSTREAM BUS

VCC

WRITE

FAULT ON DISCONNECTED

DOWNSTREAM BUS

CONNECTION FAULT

ADDRESS LTC4305

STUCK BUS

LTC4305 RESPONDS

TO ARA

ALERT

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