DOC7707 datasheet(143/307 Pages) ETC1

143 / 307 page

143

7707F–AVR–11/10

AT90USB82/162

and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-

ter mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low

when idle. Refer to Figure 16-3 and Figure 16-4 for an example. The CPOL functionality is sum-

marized below:

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or

trailing (last) edge of SCK. Refer to Figure 16-3 and Figure 16-4 for an example. The CPOL

functionality is summarized below:

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have

no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f

osc is

shown in the following table:

16.1.4

SPI Status Register – SPSR

• Bit 7 – SPIF: SPI Interrupt Flag

Table 16-2.

CPOL Functionality

CPOL

Leading Edge

Trailing Edge

Rising

Falling

Rising

Table 16-3.

CPHA Functionality

CPHA

Leading Edge

Trailing Edge

Sample

Setup

Sample

Table 16-4.

Relationship Between SCK and the Oscillator Frequency

SPI2X

SPR1

SPR0

SCK Frequency

osc/4

osc/16

osc/64

osc/128

osc/2

osc/8

osc/32

osc/64

Bit

7654

SPIF

WCOL

–

SPI2X

SPSR

Read/Write

RRRR

R/W

Initial Value

0000

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