DOC7707 datasheet(128/307 Pages) ETC1

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7707F–AVR–11/10

AT90USB82/162

Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O/8)

15.10 16-bit Timer/Counter Register Description

15.10.1

Timer/Counter1 Control Register A – TCCR1A

• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A

• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B

• Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C

The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB,

and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the

OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or

both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func-

tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,

the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-

ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or

OCnC pin must be set in order to enable the output driver.

When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is

dependent of the WGMn3:0 bits setting. Table 15-1 shows the COMnx1:0 bit functionality when

the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).

TOVn(FPWM)

and ICF n(if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOP - 1

TOP

TOP - 1

TOP - 2

Old OCRnx Value

New OCRnx Value

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

Bit

COM1A1

COM1A0

COM1B1

COM1B0

COM1C1

COM1C0

WGM11

WGM10

TCCR1A

Read/Write

R/W

Initial Value

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