AD13280SLASHPCB datasheet(17/28 Pages) AD

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AD13280

Rev. C | Page 17 of 28

EVALUATION BOARD

The AD13280 evaluation board (see Figure 20) is designed to

provide optimal performance for evaluation of the AD13280

analog-to-digital converter. The board encompasses everything

needed to ensure the highest level of performance for evaluating

the AD13280. The board requires an analog input signal, encode

clock, and power supply inputs. The clock is buffered on-board

to provide clocks for the latches. The digital outputs and out

clocks are available at the standard 40-pin connectors J1 and J2.

Power to the analog supply pins is connected via banana jacks.

The analog supply powers the associated components and the

analog section of the AD13280. The digital outputs of the

AD13280 are powered via banana jacks with 3.3 V. Contact the

factory if additional layout or applications assistance is required.

LAYOUT INFORMATION

The schematics of the evaluation board (Figure 21, Figure 22,

and Figure 23) represent a typical implementation of the

AD13280. The pinout of the AD13280 is very straightforward

and facilitates ease of use and the implementation of high

frequency/high resolution design practices. It is recommended

that high quality ceramic chip capacitors be used to decouple

each supply pin to ground directly at the device. All capacitors

can be standard, high quality ceramic chip capacitors.

Care should be taken when placing the digital output runs.

Because the digital outputs have such a high slew rate, the

capacitive loading on the digital outputs should be minimized.

Circuit traces for the digital outputs should be kept short and

should connect directly to the receiving gate. Internal circuitry

buffers the outputs of the ADC through a resistor network to

eliminate the need to externally isolate the device from the

receiving gate.

Figure 20. Evaluation Board Mechanical Layout

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