AD9884ASLASHPCB datasheet(16/24 Pages) AD

16 / 24 page

REV. C

AD9884A

–16–

1.0V

0.0V

0.5V

OFFSET = 1FH

OFFSET = 3FH

OFFSET = 0FH

OFFSET = 1FH

OFFSET = 3FH

OFFSET = 0FH

GAIN

00h

FFh

Figure 8. Gain and Offset Control

CLOCK GENERATION

A Phase Locked Loop (PLL) is employed to generate the pixel

clock. In this PLL, the HSYNC input provides a reference

frequency. A Voltage Controlled Oscillator (VCO) generates a

much higher pixel clock frequency. This pixel clock is divided

by the value PLLDIV programmed into the AD9884A, and

phase compared with the HSYNC input. Any error is used to shift

the VCO frequency and maintain lock between the two signals.

The stability of this clock is a very important element in provid-

ing the clearest and most stable image. During each pixel time,

there is a period during which the signal is slewing from the old

pixel amplitude and settling at its new value. Then there is a

time when the input voltage is stable, before the signal must

slew to a new value (Figure 9). The ratio of the slewing time to

the stable time is a function of the bandwidth of the graphics

DAC and the bandwidth of the transmission system (cable and

termination). It is also a function of the overall pixel rate.

Clearly, if the dynamic characteristics of the system remain

fixed, then the slewing and settling time is likewise fixed. This

time must be subtracted from the total pixel period, leaving the

stable period. At higher pixel frequencies, the total cycle time is

shorter, and the stable pixel time becomes shorter as well.

Any jitter in the pixel clock reduces the precision with which the

sampling time can be determined, and must also be subtracted

from the stable pixel time.

PIXEL CLOCK

INVALID SAMPLE TIMES

Figure 9. Pixel Sampling Times

Considerable care has been taken in the design of the AD9884A’s

clock generation circuit to minimize jitter. As indicated in Fig-

ure 11 and Table VI, the clock jitter of the AD9884A is less

than 5% of the total pixel time in all operating modes, making

the reduction in the valid sampling time due to jitter negligible.

The PLL characteristics are determined by the loop filter design,

by the PLL Charge Pump Current (CURRENT), and by the

VCO Range setting (VCORNGE). The loop filter design is

illustrated in Figure 10. Recommended settings of VCORNGE

and CURRENT for VESA standard display modes are listed in

Table VII.

Table V. Typical KVCO Derived From VCORNGE

Pixel Rate (MHz)

VCORNGE

KVCO (MHz/V)

20–60

100

50–90

100

80–120

150

110–140

180

0.039 F

3.3k

0.0039 F

PVD

FILT

Figure 10. PLL Loop Filter Detail

Table VI. Pixel Clock Jitter vs Frequency

Pixel Rate

Jitter p-p

(MSPS)

(ps)

(% of Pixel Time)

135

350

4.7%

108

400

4.3%

400

3.4%

450

3.4%

600

3.9%

500

2.4%

500

2.0%

550

1.8%

1000

2.5%

*AD9884A in oversampled mode.

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