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AD7671

–19–

CS, RD

SCLK

SDOUT

D15

D14

D13

X15

X14

X13

Y15

Y14

BUSY

SDIN

INVSCLK = 0

t35

t36 t37

t31

t32

t16

t33

t34

X15

X14

1617

EXT/

INT = 1

RD = 0

Figure 19. Slave Serial Data Timing for Reading (Read after Convert)

the AD7671 provides error correction circuitry that can correct

for an improper bit decision made during the first half of the

conversion phase. For this reason, it is recommended that when

an external clock is being provided, it is a discontinuous clock

that is toggling only when BUSY is LOW or, more importantly,

that does not transition during the latter half of BUSY HIGH.

External Discontinuous Clock Data Read after Conversion

Though the maximum throughput cannot be achieved using this

mode, it is the most recommended of the serial slave modes.

Figure 19 shows the detailed timing diagrams of this method.

After a conversion is complete, indicated by BUSY returning LOW,

the result of this conversion can be read while both

CS and RD

are LOW. The data is shifted out, MSB first, with 16 clock

pulses and is valid on both the rising and falling edge of the clock.

Among the advantages of this method, the conversion perfor-

mance is not degraded because there are no voltage transients

on the digital interface during the conversion process.

Another advantage is to be able to read the data at any speed up to

40 MHz, which accommodates both slow digital host interface

and the fastest serial reading.

Finally, in this mode only, the AD7671 provides a “daisy-chain”

feature using the RDC/SDIN input pin for cascading multiple

converters together. This feature is useful for reducing component

count and wiring connections when desired as, for instance, in

isolated multiconverter applications.

An example of the concatenation of two devices is shown in Fig-

ure 20. Simultaneous sampling is possible by using a common

CNVST signal. It should be noted that the RDC/SDIN input is

latched on the opposite edge of SCLK of the one used to shift out

the data on SDOUT. Therefore, the MSB of the “upstream”

converter just follows the LSB of the “downstream” converter

on the next SCLK cycle.

CNVST

SCLK

SDOUT

RDC/SDIN

BUSY

DATA

OUT

AD7671

(DOWNSTREAM)

BUSY

OUT

CNVST

SCLK

AD7671

(UPSTREAM)

RDC/SDIN

SDOUT

SCLK IN

CS IN

CNVST IN

Figure 20. Two AD7671s in a Daisy-Chain Configuration

External Clock Data Read during Conversion

Figure 21 shows the detailed timing diagrams of this method.

During a conversion, while both

CS and RD are LOW, the result

of the previous conversion can be read. The data is shifted out,

MSB first, with 16 clock pulses and is valid on both the rising and

the falling edge of the clock. The 16 bits have to be read before the

current conversion is complete. If that is not done, RDERROR

is pulsed HIGH and can be used to interrupt the host interface

to prevent incomplete data reading. There is no daisy-chain feature

in this mode, and RDC/SDIN input should always be tied either

HIGH or LOW.

REV. C

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