AD7679 datasheet(12/24 Pages) AD

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AD7671

–12–

Modes of Operation

The AD7671 features three modes of operation, Warp, Normal,

and Impulse. Each of these modes is more suitable for specific

applications.

The Warp Mode allows the fastest conversion rate up to 1 MSPS.

However, in this mode, and this mode only, the full specified accu-

racy is guaranteed only when the time between conversion does

not exceed 1 ms. If the time between two consecutive conversions

is longer than 1 ms, for instance, after power-up, the first conver-

sion result should be ignored. This mode makes the AD7671 ideal

for applications where both high accuracy and fast sample rate

are required.

The Normal Mode is the fastest mode (800 kSPS) without any limi-

tation about the time between conversions. This mode makes the

AD7671 ideal for asynchronous applications such as data acquisi-

tion systems, where both high accuracy and fast sample rate are

required.

The Impulse Mode, the lowest power dissipation mode, allows

power saving between conversions. The maximum throughput in

this mode is 666 kSPS. When operating at 100 SPS, for example,

it typically consumes only 15

mW. This feature makes the AD7671

ideal for battery-powered applications.

Transfer Functions

Using the OB/

2C digital input, the AD7671 offers two output

codings: straight binary and twos complement. The ideal transfer

characteristic for the AD7671 is shown in Figure 4 and Table III.

000...000

000...001

000...010

111...101

111...110

111...111

ANALOG INPUT

+FS – 1.5 LSB

+FS – 1 LSB

–FS + 1 LSB

–FS

–FS + 0.5 LSB

Figure 4. ADC Ideal Transfer Function

CONVERTER OPERATION

The AD7671 is a successive approximation analog-to-digital

converter based on a charge redistribution DAC. Figure 3 shows

the simplified schematic of the ADC. The input analog signal is

first scaled down and level shifted by the internal input resistive

scaler, which allows both unipolar ranges (0 V to 2.5 V, 0 V to 5 V,

and 0 V to 10 V) and bipolar ranges (

±2.5 V, ±5 V, and ±10 V).

The output voltage range of the resistive scaler is always 0 V to

2.5 V. The capacitive DAC consists of an array of 16 binary

weighted capacitors and an additional “LSB” capacitor. The

comparator’s negative input is connected to a “dummy” capacitor

of the same value as the capacitive DAC array.

During the acquisition phase, the common terminal of the array

tied to the comparator’s positive input is connected to AGND via

SWA. All independent switches are connected to the output of the

resistive scaler. Thus, the capacitor array is used as a sampling

capacitor and acquires the analog signal. Similarly, the dummy

capacitor acquires the analog signal on INGND input.

When the acquisition phase is complete and the

CNVST input goes

or is LOW, a conversion phase is initiated. When the conversion

phase begins, SWA and SWB are opened first. The capacitor array

and the dummy capacitor are then disconnected from the inputs and

connected to the REFGND input. Therefore, the differential

voltage between the output of the resistive scaler and INGND

captured at the end of the acquisition phase is applied to the

comparator inputs, causing the comparator to become unbalanced.

By switching each element of the capacitor array between REFGND

or REF, the comparator input varies by binary weighted voltage

steps (VREF/2, VREF/4 . . .VREF/65,536). The control logic toggles

these switches, starting with the MSB first, in order to bring the

comparator back into a balanced condition. After the completion

of this process, the control logic generates the ADC output code

and brings BUSY output LOW.

SWA

COMP

SWB

IND

REF

REFGND

LSB

MSB

32,768C

INGND

16,384C

CONTROL

LOGIC

SWITCHES

CONTROL

BUSY

OUTPUT

CODE

INC

INA

INB

CNVST

65,536C

Figure 3. ADC Simplified Schematic

REV. C

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