8

RF Device Data

Freescale Semiconductor, Inc.

MRFE6VP61K25HR6 MRFE6VP61K25HSR5 MRFE6VP61K25GSR5

f

(MHz)

()

()

27

12.5 + j7.00

7.00 + j0.70

40

5.75 + j5.06

5.39 + j2.62

81.36

4.04 + j5.93

4.89 + j2.95

88

2.20 + j6.70

4.90 + j2.90

98

2.30 + j6.90

4.10 + j2.50

108

2.30 + j7.00

4.40 + j3.60

144

1.60 + j5.00

3.90 + j1.50

175

1.33 + j3.90

3.50 + j2.50

230

1.29 + j3.54

2.12 + j2.68

352

0.98 + j1.45

1.82 + j2.05

500

0.29 + j1.47

1.79 + j1.80

1. Simulated data.

gate to gate, balanced configuration.

= Test circuit impedance as measured from

drain to drain, balanced configuration.

Input

Matching

Network

Device

Under

Test

Output

Matching

Network

--

--

+

+

50 

50 

Figure 12. Source and Load Impedances Optimized for IRL, Power and Efficiency — Push--Pull