M68040 datasheet(95/442 Pages) FREESCALE

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MOTOROLA

M68040 USER’S MANUAL

4- 11

4.6 MEMORY ACCESSES FOR CACHE MAINTENANCE

The cache controller in each memory unit performs all maintenance activities that supply

data from the cache to the execution units. The activities include requesting accesses to

the bus interface unit for reading new cache lines and writing dirty cache lines to memory.

The following paragraphs describe the memory accesses resulting from cache fill

operations (by both caches) and push operations (by the data cache). Refer to Section 7

Bus Operation for detailed information about the bus cycles required.

4.6.1 Cache Filling

When a new cache line is required, the cache controller requests a line read from the bus

controller. The bus controller requests a burst read transfer by indicating a line access

with the size signals (SIZ1, SIZ0) and indicates which line in the set is being loaded with

the transfer line number signals (TLN1, TLN0). TLN1 and TLN0 are undefined for the

instruction cache. These pins indicate the appropriate line numbers for data cache

transfers only. Table 4-2 lists the definition of the TLNx encoding.

Table 4-2. TLNx Encoding

TLN1

TLN0

Line

Zero

One

Two

Three

The responding device sequentially supplies four long words of data and can assert the

transfer cache inhibit signal (TCI) if the line is not cachable. If the responding device does

not support the burst mode, it should assert the TBI signal for the first long word of the line

access. The bus controller responds by terminating the line access and completes the

remainder of the line read as three, sequential, long-word reads.

Bus controller line accesses implicitly request burst mode operations from external

memory. To operate in the burst mode, the device or external hardware must be able to

increment the low-order address bits as described in Section 7 Bus Operation. The

device indicates its ability to support the burst access by acknowledging the initial long-

word transfer with transfer acknowledge (TA ) asserted and TBInegated. This procedure

causes the processor to continue to drive the address and bus control signals and to latch

a new data value for the cache line at the completion of each subsequent cycle (as

defined by TA ) for a total of four cycles. The bursting mechanism requires addresses to

wrap around so that the entire four long words in the cache line are filled in a single

operation.

When a cache line read is initiated, the first cycle attempts to load the line entry

corresponding to the instruction half-line or data item requested by the IU. Subsequent

transfers are for the remaining entries in the cache line. In the case of a misaligned

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