M68040 datasheet(51/442 Pages) FREESCALE

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M68040 USER'S MANUAL

MOTOROLA

indexing into the on-chip instruction and data caches. The MMU MDIS signal dynamically

disables address translation for emulation and diagnostic support.

Figure 3-1 illustrates the MMUs contained in the two memory units, one for instructions

(supporting instruction prefetches) and one for data (supporting all other accesses). Each

unit contains an MMU, main cache, and snoop controller. The corresponding MMUs

contain two transparent translation registers, which identify blocks of memory that can be

accessed without translation. The MMUs also contain control logic and corresponding

address translation caches (ATCs) in which recently used logical-to-physical address

translations are stored. The data memory unit contains a data write and data read buffer,

and the instruction memory unit contains an instruction line read buffer. These buffers

temporarily hold data until an opportune moment arises to write the data to external

memory or read the operand/instruction into the integer unit.

INSTRUCTION

FETCH

DECODE

CALCULATE

EXECUTE

WRITE-

BACK

FETCH

INTEGER

UNIT

CONVERT

EXECUTE

WRITE-

BACK

INSTRUCTION

ATC

INSTRUCTION

MMU/CACHE/SNOOP

CONTROLLER

BUS

CONTROL

SIGNALS

DATA

BUS

ADDRESS

BUS

DATA

ATC

DATA

MMU/CACHE/SNOOP

CONTROLLER

OPERAND DATA BUS

INSTRUCTION DATA BUS

INSTRUCTION

CACHE

DATA

CACHE

FLOATING-

POINT

UNIT

DATA MEMORY UNIT

INSTRUCTION MEMORY UNIT

INSTRUCTION

ADDRESS

DATA

ADDRESS

Figure 3-1. Memory Management Unit

The principal MMU function is to translate logical addresses to physical addresses using

translation tables stored in memory. As the MMU receives a logical address from the

integer unit, it searches its ATC for the corresponding physical address using the upper

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