PIC24FJ64GA108 datasheet(8/22 Pages) MICROCHIP

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PIC24FJ256GA110 FAMILY

DS80368N-page 8

 2008-2013 Microchip Technology Inc.

18. Module: I2C™ Module (Master Mode)

Under certain circumstances, a module operating

in Master mode may Acknowledge its own com-

mand addressed to a slave device. This happens

when the following occurs:

• 10-Bit Addressing mode is used (A10M = 1),

and:

•the I2C master has the same two upper

address bits (I2CADD<9:8>) as the addressed

slave module.

In these cases, the master also Acknowledges the

address command and generates an erroneous I2C

slave interrupt, as well as the I2C master interrupt.

Work around

Several options are available:

• When using 10-Bit Addressing mode, make

certain that the master and slave devices do not

share the same 2 MSBs of their addresses.

If this cannot be avoided:

• Clear the A10M bit (I2CxCON<10> = 0) prior to

performing a Master mode transmit.

• Read the ADD10 bit (I2CxSTAT<8>) to check

for a full 10-bit match whenever a slave I2C

interrupt occurs on the master module.

Affected Silicon Revisions

19. Module: I2C Module (Slave Mode)

Under certain circumstances, a module operating

in Slave mode may not respond correctly to some

of the special addresses reserved by the I2C

protocol. This happens when the following occurs:

• 10-Bit Addressing mode is used (A10M = 1),

and

• bits, A<7:1>, of the Slave address

(I2CADD<7:1>) fall into the range of the

reserved 7-bit address ranges, ‘1111xxx’ or

‘0000xxx’.

In these cases, the Slave module Acknowledges

the command and triggers an I2C slave interrupt; it

does not copy the data into the I2CxRCV register

or set the RBF bit.

Work around

Do not set bits, A<7:1>, of the module’s slave

address equal to ‘1111xxx’ or ‘0000xxx’.

Affected Silicon Revisions

20. Module: A/D Converter

When using PGEC1 and PGED1 to debug an

application on any 64-pin devices in this family, all

voltage references will be disabled. This includes

VREF+, VREF-, AVDD and AVSS. Any A/D conversion

will always equal 3FFh.

Work around

Use PGEC2 and PGED2 to debug any A/D

functionality.

Affected Silicon Revisions

21. Module: SPIx (Enhanced Buffer Mode)

In Enhanced Master mode, the SRMPT bit

(SPIxSTAT<7>) may erroneously become set for

several clock cycles in the middle of a FIFO transfer,

indicating that the shift register is empty when it is

not. This happens when both SPIx clock prescalers

are set to values other than their maximum

(SPIxCON<4:2> ≠ 000 and SPIxCON<1:0> ≠ 00).

Work around

Configure the module to generate an SPIx event

interrupt whenever the last bit is shifted out of the

shift register (SPIxSTAT<4:2> = 101). When the

SPIxIF flag becomes set, the shift register is

empty.

Affected Silicon Revisions

Note: This issue applies only to 64-pin devices

this

family

(PIC24FJ256GA106,

PIC24FJ192GA106 and PIC24FJ128GA106).

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