DSPIC33FJ06GS202 datasheet(7/20 Pages) MICROCHIP

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 2009-2013 Microchip Technology Inc.

DS80439M-page 7

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

9. Module: PWM

The PWM module fails to wake the CPU from

Sleep mode on a PWM Fault event.

Work around

Use the external interrupt pins to wake the CPU

from Sleep mode.

Affected Silicon Revisions

10. Module: Comparator

If the slew rate of the Comparator input signal is

lower than 198 mV/µs, the Comparator module

generates erroneous triggers/interrupts.

Work around

The Slew rate of Comparator input signal must be

higher than 198 mV/µs to avoid multiple triggers/

interrupts.

Affected Silicon Revisions

11. Module: ADC

Selecting the primary FRC (FVCO) as a clock

source for the ADC module by setting the

SLOWCLK bit (ADCON<12>) to the default setting

of ‘0’, does not work.

Work around

Always set the SLOWCLK bit (ADCON<12>) to ‘1’,

which selects the Auxiliary Clock (ACLK) as a

clock source for the ADC. Use the Auxiliary Clock

Configuration registers to select the primary FRC

(FVCO) as a source (if desired) or other clock

sources as inputs. See Section 8.0 “Oscillator

Configuration” of the device data sheet

(DS70318) for more information.

Affected Silicon Revisions

12. Module: Auxiliary Clock

When the PWMMD bit in the PMD1 register is set,

the Auxiliary Clock to both the ADC and PWM

modules is disabled.

Work around

To disable the Auxiliary clock for the PWM module

but not for the ADC module, set the individual

PWM generator PMD bits in the PMD6 register.

Affected Silicon Revisions

13. Module: Comparator

The comparator interrupt should be generated on

a rising edge of the comparator output. When

using the inverted polarity setting for the analog

comparator (CMPCONx<CMPPOL> = 1), the

interrupt should be generated when the analog

voltage at the comparator input falls below the

programmable threshold determined by the

CMPDAC register setting. However, with this

setting the interrupts may be generated regardless

of the state of the comparator.

Work around

When using comparator interrupts, configure the

external circuit to use the non-inverted polarity

comparator setting (CMPCONx<CMPPOL> = 0).

Affected Silicon Revisions

14. Module: UART

When the UART is in 4x mode (BRGH = 1) and

using two Stop bits (STSEL = 1), it may sample the

first Stop bit instead of the second one.

This issue does not affect the other UART

configurations.

Work around

Use the 16x baud rate option (BRGH = 0) and

adjust the baud rate accordingly.

Affected Silicon Revisions

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