dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

DS80439M-page 4

 2009-2013 Microchip Technology Inc.

PWM

Duty Cycle

Updates

34.

When the PWM duty cycle update coincides with the

PWM period rollover, the PWM output may be corrupted

for one PWM period.

XX

X

JTAG

Active Pull-up

35.

In JTAG mode, the TMS pin will not have an active pull-up

as required by the JTAG specification.

XX

X

SPI

Framed Master

Mode

36.

When the SPI module is configured in Framed Master

mode and the Frame Sync Pulse Edge Select bit

(FRMDLY) is set to ‘1’, transmitting a word and then

buffering another word in the SPIxBUF register before the

transmission has completed, results in an incomplete

transmission of the first data word.

XX

X

Comparator

Trigger Voltage

Level

37.

Output signal transitions occurring on the DACOUT pin

(with DAC output disabled) can cause the Comparator

trigger voltage level to change.

XX

X

CPU

Interrupt

Disable

38.

When a previous DISI instruction is active (i.e., the

DISICNT register is non-zero), and the value of the

DISICNT register is updated manually, the DISICNT

register freezes and disables interrupts permanently.

XX

X

CPU

div.sd

39.

When using the div.sd instruction, the overflow bit is not

getting set when an overflow occurs.

XX

X

UART

TX Interrupt

40.

A Transmit (TX) interrupt may occur before the data

transmission is complete.

XX

X

JTAG

Flash

Programming

41.

JTAG Flash programming is not supported.

X

X

X

PWM

Edge-Aligned

Complimentary

Mode

42.

When operating in Edge-Aligned Complimentary mode,

the dead time could become 0.

XX

X

PWM

PWM Module

Enable

43.

If the PWM Clock Divider Select register, PTCON2, is not

equal to zero, the PWM module may or may not initialize

from an override state

XX

X

PWM

PWM SWAP

44.

If the PWM is configured for Complimentary mode and the

SWAP bit is enabled, the PWM outputs might operate as

Redundant mode when the PHASE value is greater than

the programmed dead-time (DTRx) value.

XX

X

PWM

PWM in

Current-Limit

Mode

45.

A <8-ns glitch may be observed on the PWM output pins

when the Current-Limit event occurs.

XX

X

TABLE 2:

SILICON ISSUE SUMMARY (CONTINUED)

Module

Feature

Item

Number

Issue Summary

Affected

A2 A3 A4

Note 1:

Only those issues indicated in the last column apply to the current silicon revision.