AD9467 datasheet(3/5 Pages) AD

3 / 5 page

Circuit Note

CN-0227

Rev. A | Page 3 of 5

0.1µF

GAIN

0.1µF

XFMR

1:1 Z

ECT1-1-13M

ANALOG INPUT

INPUT

Z = 50Ω

Z = 2RT ║ RI

ZAAFL = RTADC ║ (RADC + 2RKB)

ZAL = 2RA + (ZAAFL ║ 2RTAMP)

ZAAFS = 2RTAMP ║ (ZO + 2RA)

ADC

INTERNAL

INPUT Z

0.1µF

ZO/2

ZAL

ZAAFS

LAAF

CAAF2

CAAF1

CAAF2

ZAAFL

RTAMP

RKB

RTAMP

RTADC

RADC

CADC

FILTER

Figure 5. Generalized Differential Amplifier/ADC Interface with Low-Pass Filter

Filter and Interface Design Procedure

In this section, a general approach to the design of the amplifier/

ADC interface with filter is presented. To achieve optimum

performance (bandwidth, SNR, and SFDR), there are certain

design constraints placed on the general circuit by the amplifier

and the ADC:

The amplifier should see the correct dc load recommended

by the data sheet for optimum performance.

The correct amount of series resistance must be used between

the amplifier and the load presented by the filter. This is to

prevent undesired peaking in the pass band.

The input to the ADC should be reduced by an external

parallel resistor, and the correct series resistance should be

used to isolate the ADC from the filter. This series resistor

also reduces peaking.

The generalized circuit shown in Figure 5 applies to most high

speed differential amplifier/ADC interfaces and will be used as

a basis for the discussion. This design approach will tend to

minimize the insertion loss of the filter by taking advantage of

the relatively high input impedance of most high speed ADCs

and the relatively low impedance of the driving source (amplifier).

The basic design process is as follows:

Select the external ADC termination resistor RTADC so that

the parallel combination of RTADC and RADC is between 200 Ω

and 400 Ω.

Select RKB based on experience and/or the ADC data sheet

recommendations, typically between 5 Ω and 36 Ω.

Calculate the filter load impedance using:

ZAAFL = RTADC || (RADC + 2RKB)

Select the amplifier external series resistor RA. Make RA less

than 10 Ω if the amplifier differential output impedance is

100 Ω to 200 Ω. Make RA between 5 Ω and 36 Ω if the output

impedance of the amplifier is 12 Ω or less.

Select RTAMP so that the total load seen by the amplifier, ZAL,

is optimum for the particular differential amplifier chosen

using the equation:

ZAL = 2RA + (ZAAFL || 2RTAMP).

Calculate the filter source resistance:

ZAAFS = 2RTAMP || (ZO + 2RA).

Using a filter design program or tables design the filter

using the source and load impedances, ZAAFS and ZAAFL,

type of filter, bandwidth, and order. Use a bandwidth that

is about 40% higher than one-half the sampling rate to

ensure flatness in the frequency span between dc and fs/2.

The internal ADC capacitance, CADC, should be subtracted

from the final shunt capacitor value generated by the

program. The program will give the value CSHUNT2 for the

differential shunt capacitor. The final common-mode

shunt capacitance is

CAAF2 = 2(CSHUNT2 − CADC).

After running these preliminary calculations, the circuit should

be given a quick review for the following items.

The value of CAAF2 should be at least 10 pF so that it is several

times larger than CADC. This minimizes the sensitivity of

the filter to variations in CADC.

The ratio of ZAAFL to ZAAFS should not be more than about 7 so

that the filter is within the limits of most filter tables and

design programs.

The value of CAAF1 should be at least 5 pF to minimize

sensitivity to parasitic capacitance and component

variations.

The inductor, LAAF, should be a reasonable value of at least

several nH.

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