CN-0227

Circuit Note

Rev. A | Page 4 of 5

In some cases, the filter design program may provide more than

one unique solution, especially with higher order filters. The

solution that uses the most reasonable set of component values

should always be chosen. Also, choose a configuration that ends

in a shunt capacitor so that it can be combined with the ADC

input capacitance.

Circuit Optimization Techniques and Trade-Offs

The parameters in this interface circuit are very interactive,

therefore, it is almost impossible to optimize the circuit for all

key specifications (bandwidth, bandwidth flatness, SNR, SFDR,

and gain). However, the peaking, which often occurs in the

Notice in Figure 6 how the pass-band peaking is reduced as the

as the value of this resistance increases, there is more signal

attenuation, and the amplifier must drive a larger signal to fill

the ADCs full-scale input range.

while reducing the bandwidth peaking, tend to slightly increase

the SNR because of the higher signal level required to drive the

ADC full scale.

distortion caused by any residual charge injection from the

internal sampling capacitor within the ADC. Increasing this

resistor also tends to reduce bandwidth peaking.

amplifier must drive a larger signal to fill the ADC input range.

Another method for optimizing the pass-band flatness is to vary

to make the net ADC input impedance between 200 Ω and 400 Ω.

Making it lower reduces the effect of the ADC input capacitance

and may stabilize the filter design; however, increases the insertion

loss of the circuit. Increasing the value also reduces peaking.

–20

–15

–10

–5

0

5

1

10

100

1000

ANALOG INPUT FREQUENCY (MHz)

10Ω

15Ω

30Ω

Figure 6. Pass-Band Flatness Performance vs. Amplifier Output Series

Balancing these trade-offs can be somewhat difficult. In this

design, each parameter was given equal weight; therefore, the

values chosen are representative of the interface performance

for all the design characteristics. In some designs, different values

may be chosen to optimize SFDR, SNR, or input drive level,

depending on system requirements.

The SFDR performance in this design is determined by two

factors: the amplifier and ADC interface component values as

shown in Figure 1, and the setting of the internal front-end

buffer bias current in the AD9467 via an internal register. The

final SFDR performance numbers shown in Table 1 and Figure 4

were obtained after following the SFDR optimization described

in the AD9467 data sheet.

Another trade-off that can be made in this particular design is

the ADC full-scale setting. The full-scale ADC differential input

voltage was set for 2 V p-p for the data obtained with this design,

which optimizes SFDR. Changing the full-scale input range to

2.5 V p-p yields about 1.5 dB improvement in SNR but slightly

degrades the SFDR performance. The input range is set by the

value loaded into an internal register in the AD9467 as described in

the data sheet.

Note that the signal in this design is ac coupled with the 0.1 μF

capacitors to block the common-mode voltages between the

amplifier, its termination resistors, and the ADC inputs. Refer to

the AD9467 data sheet for further details regarding common-

mode voltages.

Passive Component and PC Board Parasitic

Considerations

The performance of this or any high speed circuit is highly

dependent on proper PCB layout. This includes, but is not

limited to, power supply bypassing, controlled impedance lines

(where required), component placement, signal routing, and

power and ground planes. See Tutorials MT-031 and MT-101 for

more detailed information regarding PCB layout for high speed

ADCs and amplifiers.

Use low parasitic surface-mount capacitors, inductors, and

resistors for the passive components in the filter. The inductors

chosen are from the Coilcraft 0603CS series. The surface mount

capacitors used in the filter are 5%, C0G, 0402-type for stability

and accuracy.

See the CN-0227 Design Support Package for complete

documentation on the system.