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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP55231 датащи(PDF) 8 Page - Texas Instruments |
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LP55231 датащи(HTML) 8 Page - Texas Instruments |
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8 / 53 page  LP55231 SNOSCR5 – MARCH 2013 www.ti.com SERIAL BUS TIMING PARAMETERS (SDA, SCL) (1) Limit Symbol Parameter Units Min Max fSCL Clock Frequency 400 kHz 1 Hold Time (repeated) START Condition 0.6 µs 2 Clock Low Time 1.3 µs 3 Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 ns 5 Data Hold Time 50 ns 6 Data Setup Time 100 ns 7 Rise Time of SDA and SCL 20+0.1 Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1 Cb 300 ns 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START Condition 1.3 µs Capacitive Load Parameter for Each Bus Line. Cb 10 200 ns Load of One Picofarad Corresponds to One Nanosecond. (1) Specification is verified by design and is not tested in production. VEN = 1.65V to VDD. Figure 2. Timing Parameters 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP55231 |
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