LP55231 datasheet(43/53 Pages) TI

43 / 53 page

LP55231

www.ti.com

SNOSCR5 – MARCH 2013

MUX_LD_ADDR

Mux_ld_addr sets the index pointer to point the mapping table row defined by bits [6:0], but the row will not be

set active.

Name

Value (d)

Description

SRAM address

0-95

Any SRAM address containing mapping data.

Branch Instructions

BRANCH

Branch instruction is mainly indented for repeating a portion of the program code several times. Branch

instruction loads step number value to program counter. Loop count parameter defines how many times the

instructions inside the loop are repeated. The LP55231 supports nested looping, i.e., loop inside loop. The

number of nested loops is not limited. Instruction takes sixteen 32 kHz clock cycles.

Name

Accepted Value (d)

Description

loop count (i)

0-63

The number of loops to be done. “0” means an infinite loop.

step number

0-95

The step number to be loaded to program counter.

Selects the variable for loop count value. Loop count is loaded with the value of the

variable defined below.

0 = local variable A

loop count (ii)

0-3

1 = local variable B

2 = global variable C

3 = register address 3CH variable D value, or register address 42H value

INT

Send interrupt to processor by pulling the INT pin down and setting corresponding status bit high. Interrupt can

be cleared by reading interrupt bits in STATUS/INTERRUPT register at address 3A.

Name

Value

Description

No interrupt will be sent. PWM register values will remain intact.

Reset program counter value to “0” and send interrupt to processor by pulling the INT pin

int

down and setting corresponding status bit high to notify that program has ended. PWM register

values

will

remain

intact.

Interrupt

can

cleared

reading

interrupt

bits

STATUS/INTERRUPT register at address 3A.

Reset program counter value to “0” and hold. PWM register values will remain intact.

Reset program counter value to “0” and hold. PWM register values of the non-mapped drivers

will remain. PWM register values of the mapped drivers will be set to "0000 0000".

reset

On completion of int instruction with this bit set to "1" the master fader registers are set to zero

as follows: Program execution engine 1 sets MASTER FADER 1 (48H) to zero, engine 2 sets

MASTER FADER 2 (49H) to zero and engine 3 sets MASTER FADER 3 (4AH) to zero.

RST

Rst instruction resets Program Counter register (address 37H, 38H, or 39H) and continues executing the

program from the program start address defined in 4C-4E. Instruction takes sixteen 32 kHz clock cycles. Note

that default value for all program memory registers is 0000H, which is the rst instruction.

END

End program execution. Instruction takes sixteen 32 kHz clock cycles.

TRIGGER

Wait or send triggers can be used to, for example, synchronize operation between the program execution

engines. Send trigger instruction takes sixteen 32 kHz clock cycles and wait for trigger takes at least sixteen 32

kHz clock cycles. The receiving engine stores the triggers which have been sent. Received triggers are cleared

by wait for trigger instruction. Wait for trigger instruction is executed until all the defined triggers have been

received. (Note: several triggers can be defined in the same instruction.)

Submit Documentation Feedback

Product Folder Links: LP55231

LP55231 датащи(PDF) 43 Page - Texas Instruments

LP55231 датащи(HTML) 43 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

датащи скачать

ссылки URL