DAC3151 datasheet(13/57 Pages) TI

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DAC3151

DAC3161

DAC3171

www.ti.com

SLAS959A – AUGUST 2013 – REVISED AUGUST 2013

PIN ASSIGNMENT TABLE – DAC3171 14-BIT INTERFACE MODE (continued)

I/O

DESCRIPTION

NAME

NO.

DATA INTERFACE

DATA[13:0]P/N

9/10-

LVDS input data bits for both channels. Each positive/negative LVDS pair has an internal 100

19/20

termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two data

transfers per DATACKP/N clock cycle.

22/23

26/27,

The data format is interleaved with channel A (rising edge) and channel B falling edge.

29/30-

In the default mode (reverse bus not enabled):

39/40

DATA13P/N is most significant data bit (MSB)

DATA0P/N is most significant data bit (LSB)

DATACLKP/N

24/25

DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge in

multiplexed output mode.

SYNCP/N

6/7

Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising edge

of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N.

ALIGNP/N

4/5

LVPECL FIFO output syncrhonization. This positive/negative pair is captured with the rising edge of

DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it can

be left unconnected.

OUTPUT/CLOCK

DACCLKP/N

1/2

LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.

IOUTAP/N

61/60

A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full

scale current source and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input

results in a 0 mA current source and the least positive voltage on the IOUTAP pin.

REFERENCE

EXTIO

I/O

Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling

capacitor to GND when used as reference output.

BIASJ

Full-scale output current bias. For 20 mA full-scale output current, connect a 960

Ω resistor to GND.

POWER SUPPLY

IOVDD

Supply voltage for CMOS IO’s. 1.8V – 3.3V.

CLKVDD18

1.8V clock supply

DIGVDD18

21, 28

1.8V digital supply. Also supplies LVDS receivers.

VDDA18

50, 64

Analog 1.8V supply

VDDA33

55, 56,

Analog 3.3V supply

VFUSE

Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to

DVDD pins for normal operation.

51, 52,

Not Used. These pins can be left open or tied to GROUND in actual application use.

53, 54

62, 63

PACKAGE/ORDERING INFORMATION(1)

SPECIFIED

PACKAGE-

PACKAGE

LEAD/BALL

ODERING

TRANSPORT

PRODUCT

TEMPERATUR

ECO PLAN

QUANTITY

LEAD

DESIGNATOR

FINISH

NUMBER

MEDIA

E RANGE

DAC3151IRGCT

250

DAC3151

DAC3151IRGCR

2000

DAC3161IRGCT

250

GREEN (RoHS

DAC3161

QFN-64

RGC

–40°C to 85°C

NiPdAu

Tape and Reel

and no Sb/Br)

DAC3161IRGCR

2000

DAC3171IRGCT

250

DAC3171

DAC3171IRGCR

2000

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

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